PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research

PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research
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DOI:
10.1109/micro.2014.50
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发表时间:
2014-12
期刊:
2014 47th Annual IEEE/ACM International Symposium on Microarchitecture
影响因子:
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通讯作者:
Derek Lockhart;Gary Zibrat;C. Batten
Derek Lockhart;Gary Zibrat;C. Batten
中科院分区:
其他
文献类型:
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作者:
Derek Lockhart;Gary Zibrat;C. Batten

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促使建筑师考虑更大的异质性和硬件专业化的技术趋势已经越来越需要垂直整合的研究方法,这些方法可以有效地评估未来架构的绩效,领域和能源指标。到功能级别(FL),自行车级(CL)和寄存器 - 转移级别(RTL)建模。高生产力的特定域名嵌入式语言,用于并发结构建模和硬件设计。在生产力方面,有很大的好处是以更长的仿真时间来解决这个绩效生产差距,以混合的JIT汇编和JIT专业化方法,我们介绍了SIM JIT。对于CL和RTL模型。具有元追踪JIT编译器(PYPY)的解释器。生产力和可用性。
Technology trends prompting architects to consider greater heterogeneity and hardware specialization have exposed an increasing need for vertically integrated research methodologies that can effectively assess performance, area, and energy metrics of future architectures. However, constructing such a methodology with existing tools is a significant challenge due to the unique languages, design patterns, and tools used in functional-level (FL), cycle-level (CL), and register-transfer-level (RTL) modeling. We introduce a new framework called PyMTL that aims to close this computer architecture research methodology gap by providing a unified design environment for FL, CL, and RTL modeling. PyMTL leverages the Python programming language to create a highly productive domain-specific embedded language for concurrent-structural modeling and hardware design. While the use of Python as a modeling and framework implementation language provides considerable benefits in terms of productivity, it comes at the cost of significantly longer simulation times. We address this performance-productivity gap with a hybrid JIT compilation and JIT specialization approach. We introduce Sim JIT, a custom JIT specialization engine that automatically generates optimized C++ for CL and RTL models. To reduce the performance impact of the remaining unspecialized code, we combine Sim JIT with an off-the-shelf Python interpreter with a meta-tracing JIT compiler (PyPy). Sim JIT+PyPy provides speedups of up to 72× for CL models and 200× for RTL models, bringing us within 4-6× of optimized C++ code while providing significant benefits in terms of productivity and usability.