Hyper-Threading Technology Architecture and MIcroarchitecture
Hyper-Threading Technology Architecture and MIcroarchitecture
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发表时间：
2002
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通讯作者：
D. Marr
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作者：
D. Marr
英特尔的超线程技术将同步多线程的概念引入了英特尔架构。超线程技术使单个物理处理器看起来像两个逻辑处理器；物理执行资源被共享，两个逻辑处理器的架构状态被复制。从软件或体系结构的角度来看，这意味着操作系统和用户程序可以将进程或线程调度到逻辑处理器，就像在多个物理处理器上一样。从微体系结构的角度来看，这意味着来自两个逻辑处理器的指令将在共享的执行资源上同时持久和执行。本文描述了超线程技术体系结构，并讨论了英特尔首次在英特尔至强处理器家族上实施的微体系结构细节。超线程技术是英特尔企业产品线的重要补充，将被集成到各种产品中。英特尔是英特尔公司或其子公司在美国和其他国家/地区的注册商标。Xeon是英特尔公司或其在美国和其他国家/地区的子公司的商标。简介互联网和电信的惊人增长是由越来越快的系统推动的，这些系统要求越来越高的处理器性能水平。为了跟上这一需求，我们不能完全依赖传统的处理器设计方法。过去用于实现处理器性能改进的微体系结构技术--超流水线、分支预测、超标量执行、无序执行、高速缓存--已经使微处理器变得越来越复杂，拥有更多的晶体管，并且消耗了更多的功率。事实上，晶体管数量和功率的增长速度超过了处理器性能。因此，处理器架构师正在寻找方法，以比晶体管数量和功耗更快的速度提高性能。英特尔的超线程技术就是一种解决方案。处理器微体系结构处理器设计的传统方法侧重于更高的时钟速度、指令级并行(ILP)和高速缓存。实现更高时钟速度的技术包括将微体系结构流水线传输到更细的粒度，也称为超级流水线。更高的时钟频率可以通过增加每秒可以执行的指令数量来极大地提高性能。因为在超流水线微体系结构中将有更多的指令在运行，所以处理中断流水线的事件，例如高速缓存未命中、中断和分支误预测，可能代价高昂。英特尔技术期刊2002年第1季度超线程技术体系结构和微体系结构2 ILP指的是增加每个时钟周期执行的指令数量的技术。例如，超标量处理器具有多个可以同时处理指令的并行执行单元。在超标量执行的情况下，每个时钟周期可以执行几条指令。然而，对于简单的有序执行，简单地拥有多个执行单元是不够的。挑战在于找到足够的指令来执行。一种技术是无序执行，其中基于指令相关性而不是程序顺序，同时评估大的指令窗口并将其发送到执行单元。与处理器的执行速度相比，对DRAM存储器的访问速度较慢。减少这种延迟的一种技术是在处理器附近添加快速缓存。高速缓存可以提供对频繁访问的数据或指令的快速存储器访问。然而，缓存只有在很小的时候才能很快。为此，处理器通常被设计成具有高速缓存层次结构，其中快速、小型高速缓存位于非常接近处理器核心的访问等待时间并且在非常接近处理器核心的访问等待时间处操作，并且以更长的访问等待时间实现处理较不频繁访问的数据或指令的逐渐增大的高速缓存。但是，总会有需要的数据不在任何处理器缓存中的情况。处理这种高速缓存未命中需要访问存储器，并且在高速缓存未命中停止之前，处理器可能很快用完要执行的指令。从一代到下一代提高处理器性能的绝大多数技术都很复杂，而且往往会增加大量的芯片大小和功耗成本。这些技术提高了性能，但没有100%的效率；即，由于指令流中的并行性有限，将处理器中的执行单元数量增加一倍并不会使处理器的性能加倍。同样，简单地将时钟频率加倍并不能使性能加倍，因为分支错误预测会损失处理器周期数。0 5 10 15 20 25
Intel’s Hyper-Threading Technology brings the concept of simultaneous multi-threading to the Intel Architecture. Hyper-Threading Technology makes a single physical processor appear as two logical processors; the physical execution resources are shared and the architecture state is duplicated for the two logical processors. From a software or architecture perspective, this means operating systems and user programs can schedule processes or threads to logical processors as they would on multiple physical processors. From a microarchitecture perspective, this means that instructions from both logical processors will persist and execute simultaneously on shared execution resources. This paper describes the Hyper-Threading Technology architecture, and discusses the microarchitecture details of Intel's first implementation on the Intel Xeon processor family. Hyper-Threading Technology is an important addition to Intel’s enterprise product line and will be integrated into a wide variety of products. Intel is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. Xeon is a trademark of Intel Corporation or its subsidiaries in the United States and other countries. INTRODUCTION The amazing growth of the Internet and telecommunications is powered by ever-faster systems demanding increasingly higher levels of processor performance. To keep up with this demand we cannot rely entirely on traditional approaches to processor design. Microarchitecture techniques used to achieve past processor performance improvement–superpipelining, branch prediction, super-scalar execution, out-of-order execution, caches–have made microprocessors increasingly more complex, have more transistors, and consume more power. In fact, transistor counts and power are increasing at rates greater than processor performance. Processor architects are therefore looking for ways to improve performance at a greater rate than transistor counts and power dissipation. Intel’s Hyper-Threading Technology is one solution. Processor Microarchitecture Traditional approaches to processor design have focused on higher clock speeds, instruction-level parallelism (ILP), and caches. Techniques to achieve higher clock speeds involve pipelining the microarchitecture to finer granularities, also called super-pipelining. Higher clock frequencies can greatly improve performance by increasing the number of instructions that can be executed each second. Because there will be far more instructions in-flight in a superpipelined microarchitecture, handling of events that disrupt the pipeline, e.g., cache misses, interrupts and branch mispredictions, can be costly. Intel Technology Journal Q1, 2002 Hyper-Threading Technology Architecture and Microarchitecture 2 ILP refers to techniques to increase the number of instructions executed each clock cycle. For example, a super-scalar processor has multiple parallel execution units that can process instructions simultaneously. With super-scalar execution, several instructions can be executed each clock cycle. However, with simple inorder execution, it is not enough to simply have multiple execution units. The challenge is to find enough instructions to execute. One technique is out-of-order execution where a large window of instructions is simultaneously evaluated and sent to execution units, based on instruction dependencies rather than program order. Accesses to DRAM memory are slow compared to execution speeds of the processor. One technique to reduce this latency is to add fast caches close to the processor. Caches can provide fast memory access to frequently accessed data or instructions. However, caches can only be fast when they are small. For this reason, processors often are designed with a cache hierarchy in which fast, small caches are located and operated at access latencies very close to that of the processor core, and progressively larger caches, which handle less frequently accessed data or instructions, are implemented with longer access latencies. However, there will always be times when the data needed will not be in any processor cache. Handling such cache misses requires accessing memory, and the processor is likely to quickly run out of instructions to execute before stalling on the cache miss. The vast majority of techniques to improve processor performance from one generation to the next is complex and often adds significant die-size and power costs. These techniques increase performance but not with 100% efficiency; i.e., doubling the number of execution units in a processor does not double the performance of the processor, due to limited parallelism in instruction flows. Similarly, simply doubling the clock rate does not double the performance due to the number of processor cycles lost to branch mispredictions. 0 5 10 15 20 25