Assessing merged DRAM/logic technology
Assessing merged DRAM/logic technology
复制标题
评估合并的 DRAM/逻辑技术
DOI：
10.1109/iscas.1996.541917
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发表时间：
1996
期刊：
影响因子：
--
通讯作者：
Tom Chen
中科院分区：
文献类型：
--
作者：
Ytong;Tom Chen
本文介绍了DRAM工艺对内存/逻辑合并集成电路逻辑电路性能的影响，以及替代电路设计技术来抵消这种性能损失。三个最先进的逻辑进程（0.5 /spl mu/m， 0.6 /spl mu/m和0.8 /spl mu/m）和两个最先进的DRAM （64 Mb和256 Mb）进程被选择用于研究。仿真结果表明，由于DRAM过程中可用的互连层较少，导致互连延迟增加，因此在DRAM过程中逻辑电路性能下降约22%。在DRAM过程中实现逻辑电路时，根据网络和元件的数量，硅面积增加到80%。
This paper describes the impact of the DRAM process on the logic circuit performance of Memory/Logic Merged Integrated Circuits and the alternative circuit design technology to offset the performance penalty. Three state-of-the-art logic processes (0.5 /spl mu/m, 0.6 /spl mu/m, and 0.8 /spl mu/m) and two state-of-the-art DRAM (64 Mb and 256 Mb) processes have been selected for the study. The simulation results show that the logic circuit performance is degraded by about 22% on the DRAM process including increased interconnect delay due to less interconnect layers available in the DRAM process. The silicon area increased up to 80% depending on the number of nets and components when implementing the logic circuit in the DRAM process.