Metal gate-HfO/sub 2/ MOS structures on GaAs substrate with and without Si interlayer
Metal gate-HfO/sub 2/ MOS structures on GaAs substrate with and without Si interlayer
复制标题
DOI：
10.1109/led.2006.870243
复制
发表时间：
2006-02
影响因子：
4.9
通讯作者：
I. Ok;H. Kim;Manhong Zhang;C. Kang;S. Rhee;C. Choi;S. Krishnan;Tackhwi Lee;F. Zhu;G. Thareja-G.
中科院分区：
文献类型：
--
作者：
I. Ok;H. Kim;Manhong Zhang;C. Kang;S. Rhee;C. Choi;S. Krishnan;Tackhwi Lee;F. Zhu;G. Thareja-G.
In this letter, we studied the effects of post-deposition anneal (PDA) time and Si interface control layer (ICL) on the electrical characteristics of the MOS capacitor with high-/spl kappa/ (HfO/sub 2/) material on GaAs. Thin equivalent oxide thickness (EOT<3 nm) with excellent capacitance-voltage (C-V) characteristics has been obtained. The thickness of the Si ICL and PDA time were correlated with C-V characteristics. It was found that high temperature Si ICL deposition and longer PDA time at 600/spl deg/C improved the C-V shape, leakage current, and especially frequency dispersion (<5%).
