Security Checkers: Detecting processor malicious inclusions at runtime
Security Checkers: Detecting processor malicious inclusions at runtime
复制标题
安全检查器：在运行时检测处理器恶意包含
DOI：
10.1109/hst.2011.5954992
复制
发表时间：
2011
期刊：
影响因子：
--
通讯作者：
T. Levin
中科院分区：
文献类型：
--
作者：
Michael Bilzor;Ted Huffmire;C. Irvine;T. Levin
为了应对恶意颠覆对微处理器设计日益增长的威胁，非常需要简单、自动化的方法来检测这种恶意更改。基于属性规范语言(PSL)在行为验证中的应用，以及用于验证PSL断言的自动生成可综合硬件设计语言(HDL)结构的工具的出现，我们提出了一种称为安全检查器的新方法，该方法使用关注安全的PSL断言来创建硬件设计单元，用于在运行时检测恶意包含。我们描述了创建安全检查器的流程，并通过示例演示了如何使用它们来检测处理器设计中的恶意包含。由于检查器可用于模拟、FPGA模拟或作为制造设计的一部分，因此与现有方法相比，我们将说明如何使用该技术在处理器开发生命周期的更广泛部分中检测恶意包含。
To counter the growing threat of malicious subversions to the design of a microprocessor, there is a great need for simple, automated methods for detecting such malevolent changes. Based on the adoption of the Property Specification Language (PSL) for behavioral verification, and the advent of tools for automatically generating synthesizable hardware design language (HDL) constructs for verifying a PSL assertion, we propose a new method called Security Checkers, which uses security-focused PSL assertions to create hardware design units for detecting malicious inclusions at runtime. We describe the process flow for creating Security Checkers and demonstrate by example how they can be used to detect malicious inclusions in a processor design. Because the checkers can be used in simulation, FPGA emulation, or as part of a fabricated design, we illustrate how this technique can be used to detect malicious inclusions over a much broader segment of the processor development lifecycle, compared to existing methods.