A low-power integrated neural interface with digital spike detection and extraction
A low-power integrated neural interface with digital spike detection and extraction
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DOI：
10.1007/s10470-009-9371-1
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发表时间：
2010-07-01
影响因子：
1.4
通讯作者：
Sawan, Mohamad
中科院分区：
文献类型：
--
作者：
Gosselin, Benoit;Sawan, Mohamad
我们提出了一个集成的神经接口的设计，用于多通道神经记录。该设计具有处理神经信号调节、数字化、时分复用的混合信号部分，以及提供控制、绝对阈值检测、尖峰提取和与主机接口串行通信的数字模块。检测和提取策略通过同步的内部数据缓冲来保留整个神经元尖峰波形。该带宽减少方案提示更好的波形分选结果和改善的假肢应用性能。提出的神经接口的两个部分分别制作在CMOS 0.18 μ m工艺。整个神经接口具有16个通道用于验证，但是，所提出的方法可扩展到更大的通道数。实现的神经接口的性能进行了验证与合成神经波形的测试台。它的特点是每通道功耗为138 μ W，尺寸为2.304 mm（2），带宽降低系数高达48。
We present the design of an integrated neural interface intended for multi-channel neural recording. The design features a mixed-signal part that handles neural signal conditioning, digitization, time-division multiplexing, and a digital module providing control, absolute threshold detection, extraction of spikes, and serial communications towards a host interface. The detection and extraction strategy preserves the entire neuronal spike waveshapes by means of synchronized internal data buffering. This bandwidth reduction scheme prompts for better waveform sorting results and improved performance in prosthetic applications. Both parts of the presented neural interface were fabricated separately in a CMOS 0.18 mu m process. The whole neural interface features 16 channels for validation, but, the proposed approach is scalable to larger channel counts. The performance of the implemented neural interface was validated on testbench with synthetic neural waveforms. It features a power consumption of 138 mu W per channel and a size of 2.304 mm(2), and achieves a bandwidth reduction factor of up to 48.