Introduction to the special issue on Networks-on-Chip ( NoC ) of the Journal of Parallel and Distributed Computing ( JPDC )
Introduction to the special issue on Networks-on-Chip ( NoC ) of the Journal of Parallel and Distributed Computing ( JPDC )
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并行与分布式计算杂志 (JPDC) 片上网络 (NoC) 特刊简介
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
R. Das
中科院分区：
文献类型：
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作者：
Asit K. Mishra;Aditya Yanamandra;R. Das
我们非常高兴向《并行与分布式计算杂志》(JPDC) 的读者介绍有关片上网络 (NoC) 的特刊。本期特刊由八篇经过同行评审的论文组成，涵盖了片上网络设计的广泛主题。根据预计的技术路线图，基于多核和多处理器的大型片上系统 (MPSoC) 架构将轻松包含数十亿个晶体管。在单个芯片上集成同时运行的数百个内核的复杂性要求迫切需要重新审视片上通信基础设施。能够有效解决和克服设计问题的新片上通信范式称为片上网络（NoC）范式。本期特刊重点关注如何应对当前和未来可扩展多核架构中的片上网络 (NoC) 带来的一些设计挑战。 NoC范式提供了可扩展的基础设施，我们可以利用它在单个芯片上集成大量计算逻辑和存储块。虽然传统的基于总线的网络和点对点网络可以提供通信带宽，但它们会遇到功耗增加以及争用或延迟问题。因此，片上网络范式是从拥有可轻松扩展和模块化扩展的基础设施的愿望演变而来的。借助模块化和常规通信路径，片上网络可实现路径多样性、可重用性和可预测性，将其组合起来可减少网络拥塞、减轻功耗并提供增强的可靠性。手机、无线芯片组、便携式多媒体和手机只是使用 MPSoC 的少数应用。在这些能源受限的环境中，底层通信结构 (NoC) 的性能、功耗和传输、可靠性、容错、错误恢复和硬件成本构成了严峻的设计挑战。此外，实施、测试、产量、建模和服务质量（QoS）也与这些系统的实际实现相关。随着技术的扩展，对片上网络金属互连及其可扩展至亚纳米领域的担忧也在争论之中。为了探索研究界如何积极应对这些挑战，本期特刊汇集了来自学术界和工业界的杰出专家，他们在片上网络设计领域做出了重大贡献。特别部分的第一篇论文是“RAFT：一种用于片上网络频率调谐的路由器架构”，作者为 Asit K. Mishra、Aditya Yanamandra、Reetuparna Das、Soumya Eachempati、Ravi Iyer、N. Vijaykrishnan 和 Chita R. Das。在本文中，作者建议最大限度地减少功耗
It is with great pleasure that we introduce the special issue on Networks-on-Chip (NoC) to the readers of the Journal of Parallel and Distributed Computing (JPDC). This special issue consists of eight peer-reviewed papers that cover a wide spectrum of topics in NoC design. Large multicore-based and multiprocessor-based systems-onchip (MPSoC) architectures will easily consist of billions of transistors according to projected technology roadmaps. The complexity in integrating hundreds of cores running simultaneously on a single chip calls for a serious need to revisit the on-chip communication infrastructure. The new on-chip communication paradigm that can effectively address and overcome the design issues is called theNetworks-on-Chip (NoC) paradigm. This special issue focuses on how to meet some of the design challenges posed by current and future NoCs in scalable multicore architectures. The NoC paradigm provides the scalable infrastructure with which we can integrate a large number of computational logic and storage blocks on a single chip. While traditional bus-based networks and point-to-point networks can provide communication bandwidth, they suffer from increased power dissipation and contention or latency issues. Therefore, the NoC paradigm has evolved from the desire to have an infrastructure that can be easily scaled and modularly expanded. With modular and regular communication paths, NoCs enable path diversity, reusability and predictability, which, when combined, reduce network congestion, alleviate power dissipation, and provide enhanced reliability. Mobile handsets, wireless chipsets, portable multimedia and cell phones are just a few applications which make use of MPSoC. In these energy-constrained environments, performance, power consumption and delivery, reliability, fault tolerance, error recovery and hardware costs of the underlying communication fabric (NoC) are posing serious design challenges. Moreover, implementation, testing, yield, modeling and quality of service (QoS) are also related to the practical realization of these systems. With technology scaling, concerns aboutmetallic interconnects for NoC and their scalability into the subnanometer regime are also being debated. With the goal of exploring how the research community is aggressively meeting these challenges, this special issue brings together outstanding experts from both academia and industry who have made significant contributions to the area of NoC design. The first paper in the special section is ‘‘RAFT: A Router Architecture with Frequency Tuning for On-chip Networks’’, by Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi Iyer, N. Vijaykrishnan, and Chita R. Das. In this paper, the authors propose to minimize the power dissipation in