Understanding soft errors in uncore components
Understanding soft errors in uncore components
复制标题
了解非核心组件中的软错误
DOI：
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
S. Mitra
中科院分区：
文献类型：
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作者：
Hyungmin Cho;Chen;Thomas Shepherd;S. Mitra
软错误对处理器内核的影响已经得到了广泛的研究。然而，关于片上系统（SoC）的非核心组件（例如存储器子系统和I/O控制器）中的软错误的报道很少。在这项工作中，我们研究如何在非核心组件的软错误影响系统级的行为。我们已经创建了一个新的混合模式仿真平台，它结合了两个不同抽象级别的仿真器，并实现了20，000倍的RTL仿真加速。使用这个平台，我们提出了第一个研究的系统级影响的软错误内部的各种非核心组件的大规模，多核SoC使用工业级，开源的OpenCRT2 SoC设计。我们的研究结果表明，在非核心组件的软错误可以显着影响系统级的可靠性。我们还表明，非核心软错误可以创建传统的系统级检查点恢复技术的重大挑战。为了克服这样的恢复挑战，我们提出了一个新的重放恢复技术属于内存子系统的非核心组件。对于OpenSSL T2的L2缓存控制器和DRAM控制器组件，我们的新技术将应用程序运行因软错误而无法产生正确结果的概率降低了100倍以上，芯片级面积和功耗影响分别为3.32%和6.09%。
The effects of soft errors in processor cores have been widely studied. However, little has been published about soft errors in uncore components, such as memory subsystem and I/O controllers, of a System-on-a-Chip (SoC). In this work, we study how soft errors in uncore components affect system-level behaviors. We have created a new mixed-mode simulation platform that combines simulators at two different levels of abstraction, and achieves 20,000× speedup over RTL-only simulation. Using this platform, we present the first study of the system-level impact of soft errors inside various uncore components of a large-scale, multi-core SoC using the industrial-grade, open-source OpenSPARC T2 SoC design. Our results show that soft errors in uncore components can significantly impact system-level reliability. We also demonstrate that uncore soft errors can create major challenges for traditional system-level checkpoint recovery techniques. To overcome such recovery challenges, we present a new replay recovery technique for uncore components belonging to the memory subsystem. For the L2 cache controller and the DRAM controller components of OpenSPARC T2, our new technique reduces the probability that an application run fails to produce correct results due to soft errors by more than 100× with 3.32% and 6.09% chip-level area and power impact, respectively.