Reduced-Complexity Soft-Output Viterbi Algorithm for Channels Characterized by Dominant Error Events
Reduced-Complexity Soft-Output Viterbi Algorithm for Channels Characterized by Dominant Error Events
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DOI：
10.1109/glocom.2010.5683223
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发表时间：
2010-12
期刊：
影响因子：
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通讯作者：
R. Motwani;T. Souvignier
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文献类型：
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作者：
R. Motwani;T. Souvignier
提出了一种在信道比特上产生软输出或对数似然比（LLR）的算法，该算法可以由主导错误事件（DEE）来表征。磁记录和光学记录系统属于这类通道[5]。对于这些信道，通常使用由外部Reed-Solomon（RS）和具有单个奇偶校验位或多个奇偶校验位的内部奇偶校验码组成的级联编码方案。内部奇偶校验码通常不使用网格来解码以限制计算开销。相反，通过使用包括滤波器组的后处理器来解码奇偶校验码。提出了一种利用信息重用来降低内部奇偶校验码译码复杂度的后处理器。然后开发后处理器的变体以使得能够基于DEE生成软输出。如果选择适当的主要错误事件列表，软输出算法的性能接近于软输出维特比算法（SOVA）。其优点是与SOVA相比，计算成本要低得多。从概念上讲，所提出的降低复杂度的SOVA不考虑网格中的所有路径来计算软输出，而是仅使用基于DEE的路径来生成软输出。
An algorithm to generate soft output or log-likelihood-ratios (LLR''s) on channel bits for channels which can be characterized by dominant error events (DEE) is proposed. The magnetic recording and optical recording systems fall under such class of channels [5]. For these channels, a concatenated coding scheme consisting of an outer Reed-Solomon (RS) and an inner parity code with single bit parity or multiple parity bits is commonly used. The inner parity code is usually not decoded using a trellis to limit the computation overhead. Instead, the parity code is decoded by using a post-processor which comprises of a bank of filters. The reduced complexity post-processor using information reuse for decoding the inner parity code is first proposed. A variant of the post-processor is then developed to enable generate soft-output based on the DEE. The performance of the soft-output algorithm is close to the Soft-Output Viterbi Algorithm (SOVA), if the dominant error event list is appropriately chosen. The advantage is that the computational cost is much lesser compared to the SOVA. Conceptually, the proposed reduced-complexity SOVA does not consider all the paths in the trellis for computing the soft-output, rather it uses only on the DEE based paths to generate the soft output.