Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator
Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator
复制标题
DOI：
10.1109/tc.2014.2315627
复制
发表时间：
2014-08
影响因子：
3.7
通讯作者：
A. Pedram;A. Gerstlauer;R. V. D. Geijn
中科院分区：
文献类型：
--
作者：
A. Pedram;A. Gerstlauer;R. V. D. Geijn
本文研究了将密集的线性系统和线性最小二乘问题求解到自定义线性代数处理器时遇到的算法的映射。具体而言，重点是Cholesky，Lu（具有部分枢轴）和QR因素化及其阻塞算法。作为研究的一部分，我们暴露了重新设计浮点单元及其周围数据路径的好处，以支持这些复杂的操作。我们展示了如何增加体系结构中等复杂性，从而大大减轻了算法中的复杂性。我们研究设计权衡及其建筑修改的有效性，以证明我们可以将功率和性能效率提高到否则只能预期的全面ASIC设计的水平。内核的可行性研究扩展到阻塞水平，并表明，在块水平上，线性代数核（LAC）可以实现高效率，对于Cholesky和Lu分解，最多45 Gflops/w，超过35 Gflops/W gflops/W用于QR分解。在维持此类效率的同时，我们对MAC单元的扩展可以分别实现高达10％，12％和20％的速度，分别为Cholesky，Lu和QR分解的阻止算法。
This paper examines the mapping of algorithms encountered when solving dense linear systems and linear least-squares problems to a custom Linear Algebra Processor. Specifically, the focus is on Cholesky, LU (with partial pivoting), and QR factorizations and their blocked algorithms. As part of the study, we expose the benefits of redesigning floating point units and their surrounding data-paths to support these complicated operations. We show how adding moderate complexity to the architecture greatly alleviates complexities in the algorithm. We study design tradeoffs and the effectiveness of architectural modifications to demonstrate that we can improve power and performance efficiency to a level that can otherwise only be expected of full-custom ASIC designs. A feasibility study of inner kernels is extended to blocked level and shows that, at block level, the Linear Algebra Core (LAC) can achieve high efficiencies with up to 45 GFLOPS/W for both Cholesky and LU factorization, and over 35 GFLOPS/W for QR factorization. While maintaining such efficiencies, our extensions to the MAC units can achieve up to 10, 12, and 20 percent speedup for the blocked algorithms of Cholesky, LU, and QR factorization, respectively.