Improving and extending the algebraic approach for verifying gate-level multipliers
Improving and extending the algebraic approach for verifying gate-level multipliers
复制标题
改进和扩展验证门级乘法器的代数方法
DOI：
--
复制
发表时间：
2018
期刊：
影响因子：
--
通讯作者：
Manuel Kauers
中科院分区：
文献类型：
--
作者：
Daniela Ritirc;Armin Biere;Manuel Kauers
目前验证门级乘法器最有效的方法是使用计算机代数。它减少了一个字级乘法器规格的Grobner基础来自门级实现。当且仅当电路是乘法器时，这种减少产生零。我们通过提取全加器和半加器约束来减少Grobner基，从而大大加快计算速度，从而改进了这种方法。根据部分产品而不是输入来重构规范会产生进一步的改进。作为第三个贡献，我们扩展这些代数技术来验证位级乘法器的等效性，而不使用字级规范。
The currently most effective approach for verifying gate-level multipliers uses Computer Algebra. It reduces a word-level multiplier specification by a Grobner basis derived from a gate-level implementation. This reduction produces zero if and only if the circuit is a multiplier. We improve this approach by extracting full- and half-adder constraints to reduce the Grobner basis, which speeds up computation substantially. Refactoring the specification in terms of partial products instead of inputs yields further improvements. As a third contribution we extend these algebraic techniques to verify the equivalence of bit-level multipliers without using a word-level specification.