Comparison of lateral and vertical DMOS specific on-resistance
Comparison of lateral and vertical DMOS specific on-resistance
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DOI：
10.1109/iedm.1985.191081
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发表时间：
1985
期刊：
影响因子：
--
通讯作者：
M. Amato;V. Rumennik
中科院分区：
文献类型：
--
作者：
M. Amato;V. Rumennik
横向和垂直DMOS晶体管的特定导通电阻特性在50和800伏电压之间进行了比较。回顾了垂直DMOS晶体管的击穿和导通电阻关系，然后对横向DMOS晶体管的击穿和导通电阻特性进行了建模。然后在垂直装置和横向装置之间进行直接比较。结果表明，垂直器件在低电压下具有较低的比导通电阻，因为它具有较高的通道宽度/单位芯片面积封装。在较高的电压下，由于横向器件能够保持较高的漂移区电导率，因此它等于或优于垂直器件。
The specific on-resistance characteristics of the lateral and vertical DMOS transistors are compared for voltages between 50 and 800 volts. The vertical DMOS transistor's breakdown and on-resistance relationship is reviewed, followed by modeling results of the lateral DMOS transistor's breakdown and on-resistance characteristics. A direct comparison is then made between the vertical and lateral devices. The results indicate that the vertical device has lower specific on-resistance at low voltages because of its higher channel width/unit chip area packing. At higher voltages, the lateral device becomes equal to or better than the vertical device because of its ability to maintain a high drift region conductivity.