10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS
10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS
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10.7 105GOPS 36mm2 异构 SDR MPSoC，具有能量感知动态调度和迭代检测解码功能，适用于 65nm CMOS 中的 4G
DOI：
10.1109/isscc.2014.6757394
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
R. Schüffny
中科院分区：
文献类型：
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作者：
Benedikt Noethen;Oliver Arnold;Esther P. Adeva;Tobias Seifert;E. Fischer;S. Kunze;E. Matús;G. Fettweis;H. Eisenreich;G. Ellguth;S. Hartmann;S. Höppner;S. Schiefer;J.;Stefan Scholze;D. Walter;R. Schüffny
现代移动通信系统面临着相互矛盾的设计约束。一方面，不断增加的传输模式种类需要高度灵活的解决方案，以支持日益增长的应用需求数量和多样性。另一方面，在满足苛刻的性能要求的同时，必须考虑严格的功率限制（例如，在毫微微基站和终端处）。为了解决这些问题，现有的软件定义无线电（SDR）平台，例如[1 - 2]，提出了一种具有异构处理元件（PE）阵列的多处理器片上系统（MPSoC）。MPSoC解决方案提供可编程性和并行性，从而产生灵活性、处理性能和功率效率。为了调度资源并应用电源门控，采用了一种静态方法。相比之下，我们提出了一种具有运行时调度和细粒度分层电源管理的异构MPSoC平台（Tomahawk2）。该解决方案能够完全适应现代并发无线应用中动态变化的工作负载和半确定性行为。所提出的动态调度器（CoreManager，CM）既可以在通用处理器上以软件形式实现，也可以在专用的特定应用硬件单元上实现。显然，软件方法提供了最高程度的灵活性；然而，对于复杂应用，它可能成为性能瓶颈。[3]中提出了一种高吞吐量的专用集成电路（ASIC），但该解决方案不允许调整调度算法。在这项工作中，通过在专用指令集处理器（ASIP）上实现CM克服了这些限制。
Modern mobile communication systems face conflicting design constraints. On the one hand, the expanding variety of transmission modes calls for highly flexible solutions supporting the ever-growing number and diversity of application requirements. On the other hand, stringent power restrictions (e.g., at femto base stations and terminals) must be considered, while satisfying the demanding performance requirements. In order to cope with these issues, existing SDR platforms, e.g. [1-2], propose an MPSoC with a heterogeneous array of processing elements (PEs). MPSoC solutions provide programmability and parallelism yielding flexibility, processing performance and power efficiency. To schedule the resources and to apply power gating, a static approach is employed. In contrast, we present a heterogeneous MPSoC platform (Tomahawk2) with runtime scheduling and fine-grained hierarchical power management. This solution can fully adapt to the dynamically varying workload and semi-deterministic behavior in modern concurrent wireless applications. The proposed dynamic scheduler (CoreManager, CM) can be implemented either in software on a general-purpose processor or on a dedicated application-specific hardware unit. It is evident that the software approach offers the highest degree of flexibility; however, it may become a performance-bottleneck for complex applications. A high-throughput ASIC was presented in [3], but this solution does not permit scheduling algorithms to be adjusted. In this work, these limitations are overcome by implementing the CM on an ASIP.