Design Considerations for Sub-90-nm Split-Gate Flash-Memory Cells
Design Considerations for Sub-90-nm Split-Gate Flash-Memory Cells
复制标题
DOI：
10.1109/ted.2007.907265
复制
发表时间：
2007-10
影响因子：
3.1
通讯作者：
S. Saha
中科院分区：
文献类型：
--
作者：
S. Saha
本文提出了一种系统的方法来设计有效的子90纳米分裂栅闪存单元和优化的细胞性能在目前已知的缩放约束。器件模拟结果表明，通过适当优化沟道结构、非对称晕掺杂分布和浅源漏结，可以实现高性能亚90 nm分裂栅单元。在本文中，晕和沟道掺杂分布进行了优化，以实现有效的单元编程的目标漏极编程电压Vsp = 6.5 V，而保持击穿电压BV > Vsp与可容忍的泄漏电流。结果表明，采用适当优化的工艺参数，可以实现65 nm分裂栅Flash存储器，其单元读电流Ir 1 ap 235 μ m，编程单元漏电流Ir 0 < 2.2 nA/μ m，编程时间ap 30 μ s，和擦除时间ap 40 μ s。本文清楚地表明了高性能65纳米分裂栅闪存单元的可行性。
This paper presents a systematic methodology to design efficient sub-90-nm split-gate Flash-memory cells and optimize the cell performance within the presently known scaling constraints. The device-simulation results show that the high-performance sub-90-nm split-gate cells can be realized by a proper optimization of the channel and asymmetric halo-doping profiles and shallow source/drain junctions. In this paper, the halo-and channel-doping profiles were optimized to achieve the target drain-programming voltage Vsp = 6.5 V for an efficient cell programming, whereas keeping the breakdown voltage BV > Vsp with tolerable leakage currents. It is shown that, using the properly optimized technology parameters, 65-nm split-gate Flash memory can be achieved with cell-read current, Ir1 ap 235 mum, programmed cell-leakage current, Ir0 < 2.2 nA/ mum at the read condition, time-to-program ap 30 mus, and time-to-erase ap 40 mus. This paper clearly demonstrates the feasibility of high-performance 65-nm split-gate Flash-memory cells.