3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS
3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS
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3.2 多标准 185fsrms 0.3 至 28Gb/s 40dB 背板信号调节器，采用 28nm CMOS 封装，具有自适应模式匹配 36-Tap DFE 和数据速率调整 PLL
DOI：
10.1109/isscc.2015.7062922
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发表时间：
2015
期刊：
影响因子：
--
通讯作者：
K. Higeta
中科院分区：
文献类型：
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作者：
T. Kawamoto;T. Norimatsu;K. Kogo;F. Yuki;N. Nakajima;M. Tsuge;T. Usugi;Tomofumi Hokari;H. Koba;Takemasa Komori;Junya Nasu;Tsuneo Kawamata;Yuichi Ito;Seiichi Umai;J. Kumazawa;Hiroaki Kurahashi;T. Muto;T. Yamashita;M. Hasegawa;K. Higeta
为了支持数据丰富的业务，需要加快处理速度和网络速度，在保持信道长度和多速率链路的同时，需要增加背板互连的带宽。然而，在高数据速率下，信道损耗和阻抗不连续增加，使得信道补偿变得困难。在这项工作中，我们的目标串行链路从0.3Gb/s的100G-KR4自动协商到28.05Gb/s的32GFC 40dB背板架构。要实现这一挑战，有两个关键技术。首先，我们引入了一个36分路的决策反馈均衡器（DFE）来消除由于连接器产生的反射，因为这些反射会使眼睛闭上。为了操作36抽头DFE，我们需要固定一个CDR锁定点并准确计算36抽头系数。因此，我们开发了一个带有4b模式滤波器的模式捕获CDR来固定锁定点，以及一个3b模式匹配的自适应均衡器（AEQ）来优化36个分接系数。这些技术使我们的芯片能够补偿40dB的信道损耗。其次，我们的目标是100G-KR4/40G-KR4/10G-KR/25G-KR和32GFC/16GFC/8GFC/4GFC。为了在0.3至28.05Gb/s的宽数据速率范围内以低抖动运行，我们开发了一个具有两个lc -VCO和一个环形VCO的锁相环架构，通过控制LDO来实现数据速率调整技术。我们的测试芯片是用28纳米CMOS制造的。我们的信号调节器是实现BER <；1012 PRBS31在100G-KR4下，在40dB芯片对芯片背板上使用两个连接器，使用36分接DFE来消除反射，并在0.3至28.05Gb/s的广泛数据速率范围内工作。
As processing and network speeds are accelerated to support data-rich services, the bandwidth of backplane interconnects needs to be increased while maintaining the channel length and multi-rate links. However, channel losses and impedance discontinuities increase at high data-rates, making it difficult to compensate the channel. In this work, we target serial links from auto-negotiation in 100G-KR4 of 0.3Gb/s to 32GFC of 28.05Gb/s in 40dB backplane architecture. To achieve this challenge, there are two key techniques. First, we introduce a 36-tap decision-feedback equalizer (DFE) to cancel reflections due to connectors because these reflections close the eye. To operate the 36-tap DFE, we need to fix a CDR lock-point and calculate 36-tap coefficients accurately. Thus, we develop a pattern-captured CDR with a 4b pattern filter to fix the lock-point, and a 3b pattern-matched adaptive equalizer (AEQ) to optimize 36 tap coefficients. These techniques enable our chip to compensate 40dB channel loss. Second, we target 100G-KR4/40G-KR4/10G-KR/25G-KR and 32GFC/16GFC/8GFC/4GFC. To operate across a wide range of data-rates, from 0.3 to 28.05Gb/s, with low jitter, we develop a PLL architecture with two LC-VCOs and one ring VCO with a data-rate-adjustment technique by controlling an LDO. Our test chip is fabricated in 28nm CMOS. Our signal conditioner is the demonstration to achieve the BER <;1012 PRBS31 at 100G-KR4 in a 40dB chip-to-chip backplane with two connectors by using the 36-tap DFE to cancel the reflection and to operate across a wide range of data-rates from 0.3 to 28.05Gb/s.
自适应位宽控制的AR均衡电路功耗降低技术
DOI：
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发表时间：
2004
期刊：
IEICE Technical Report CAS2004-16, VLD2004-27, SIP2004-30
影响因子：
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作者：
Kousuke Tarumi;et. al.
通讯作者：
et. al.