Realization of high breakdown voltage (>700 V) in thin SOI devices
Realization of high breakdown voltage (>700 V) in thin SOI devices
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DOI：
10.1109/ispsd.1991.146060
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发表时间：
1991-04
期刊：
影响因子：
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通讯作者：
S. Merchant;E. Arnold;H. Baumgart;S. Mukherjee;H. Pein;R. Pinker
中科院分区：
文献类型：
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作者：
S. Merchant;E. Arnold;H. Baumgart;S. Mukherjee;H. Pein;R. Pinker
从理论上和实验上研究了绝缘体上硅（SOI）横向二极管的雪崩击穿电压。理论上，推导了实现均匀横向电场从而优化击穿电压的条件。利用该条件，可以看出，对于低于约1μm的SOI厚度，二极管击穿电压随着SOI层厚度的减小而增加。实验上，首次证明具有约 0.1μm 厚的 SOI 层和 2μm 厚的掩埋氧化层的二极管具有超过 700V 的击穿电压。获得的结果证明了制造高压薄膜SOI LDMOS晶体管的可行性，更重要的是，证明了将此类器件与高性能超薄SOI CMOS电路集成在单个芯片上的能力。>
The avalanche breakdown voltage of silicon on insulator (SOI) lateral diodes is investigated theoretically and experimentally. Theoretically, a condition is derived for achieving a uniform lateral electric field and thus optimizing the breakdown voltage. Using this condition, it is shown that, for SOI thicknesses below about 1 mu m, diode breakdown voltage increases with decreasing SOI layer thickness. Experimentally, breakdown voltages in excess of 700 V have been demonstrated for the first time on diodes having approximately 0.1- mu m-thick SOI layers and 2- mu m-thick buried oxide layers. The results obtained demonstrate the feasibility of making high-voltage thin-film SOI LDMOS transistors and, more importantly, the ability to integrate such devices with high-performance ultra-thin SOI CMOS circuits on a single chip.>