Noise Immunity of Desat Protection Circuitry for High Voltage SiC MOSFETs with High dv/dt
Noise Immunity of Desat Protection Circuitry for High Voltage SiC MOSFETs with High dv/dt
复制标题
高 dv/dt 高压 SiC MOSFET 去饱和保护电路的噪声抗扰度
DOI：
10.1109/apec42165.2021.9487072
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发表时间：
2021
期刊：
影响因子：
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通讯作者：
William Giewont
中科院分区：
文献类型：
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作者：
Xingxuan Huang;Shiqi Ji;Cheng Nie;Dingrui Li;Min Lin;L. Tolbert;Fred Wang;William Giewont
本文从抗扰度的角度分析了高压（>3.3 kV） SiC mosfet的防沙保护。高电压SiC mosfet产生的高正dv/dt和长电压上升时间是对土壤保护电路抗噪性的主要威胁。分析了寄生电感、阻尼电阻、箝位阻抗等多种影响因素的影响。在某些情况下，高dv/dt的漏极与保护电路之间的小寄生电容（<0.01 pF）决定了高阻抗分压器保护电路的抗噪能力。定量导出了噪声抗扰度，指导了噪声抗扰度的提高。提出了增加屏蔽层、减小箝位阻抗、减小分压器阻抗等增强抗扰度的方法，并通过实验验证了方法的有效性。
This paper provides an analysis of the desat protection for high voltage (>3.3 kV) SiC MOSFETs from the perspective of noise immunity. The high positive dv/dt with long voltage rise time generated by high voltage SiC MOSFETs is identified as a major threat to noise immunity of the desat protection circuitry. The impact of numerous influencing factors is analyzed, such as parasitic inductance, damping resistance, and clamping impedance. In some cases, small parasitic capacitances (<0.01 pF) between the drain terminal with high dv/dt and protection circuitry dominate the noise immunity of the desat protection circuitry with high-impedance voltage divider. The noise immunity margin is derived quantitatively to guide the noise immunity improvement. Different noise immunity enhancement methods are developed and validated with experimental results, including adding a shielding layer, reducing clamping impedance, and decreasing voltage divider impedance.