Ultralow-power LSI Technology with Silicon on Thin Buried Oxide (SOTB) CMOSFET
Ultralow-power LSI Technology with Silicon on Thin Buried Oxide (SOTB) CMOSFET
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采用薄埋氧化物硅 (SOTB) CMOSFET 的超低功耗 LSI 技术
DOI：
10.5772/6877
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
N. Sugii
中科院分区：
文献类型：
--
作者：
T. Ishigaki;R. Tsuchiya;Y. Morita;N. Sugii
对于从移动的到高性能计算的各种应用，超大规模集成（VLSI）电路的功耗是一个严重的问题。长期以来，缩放规则一直是VLSI电路中互补金属氧化物半导体（CMOS）场效应晶体管（FET）的优化范例。在理想的缩放规则中，电源电压Vdd应与晶体管的小型化成比例地减小。到目前为止，这一削减措施基本上是成功的。然而，在尺寸极度缩小的晶体管中，例如45纳米逻辑节点及以上的晶体管，进一步降低Vdd非常困难。除非使用缩放规则来降低功耗，否则LSI的功耗将由于操作和待机泄漏功率的增加而显著增加（Sakurai，2004; Chen，2006）。这种困难的主要原因被广泛认为是CMOSFET的阈值电压（Vth）变化的增加，因为考虑到增加的Vth变化的裕度，应该将Vth设置得更高（Takeuchi等人，1997年）。晶体管特性的变化，主要是Vth变化，在亚100纳米技术中显著增加。这使得缩放规则所要求的功耗降低变得困难，并且显著增加了LSI芯片的功耗。这里，作为代表性LSI单元电路的反相器的功耗P被定义为：
For a variety of applications from mobile to high-performance computing, the power consumption of very-large-scale-integrated (VLSI) circuits is a serious issue. The scaling rule has been a paradigm for miniaturizing complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) in VLSI circuits for a long period. In the ideal scaling rule, the supply voltage Vdd should decrease in proportion to the miniaturization of the transistor. This Vdd reduction has roughly been successful so far. In extremely scaled transistors such as those in the 45-nm logic node and beyond, however, it is very difficult to further decrease Vdd. Unless Vdd is reduced with the scaling rule, the power consumption of the LSI will increase significantly due to an increase in both operational and standby-leakage power (Sakurai, 2004; Chen, 2006). The primary cause of this difficulty is widely recognized as the increase in threshold voltage (Vth) variation of CMOSFETs, because Vdd should be set higher considering the margin to the increased Vth variation (Takeuchi et al., 1997). Variation of transistor characteristics, primarily Vth variation, is increasing substantially in sub-100-nm technologies. This makes the Vdd reduction, required by the scaling rule, difficult, and significantly increases the power consumption of an LSI chip. Here, power consumption P of an inverter, which is the representative LSI unit circuit, is defined as