Digital IP protection using threshold voltage control
Digital IP protection using threshold voltage control
复制标题
使用阈值电压控制的数字 IP 保护
DOI：
--
复制
发表时间：
2016
期刊：
影响因子：
--
通讯作者：
S. Vrudhula
中科院分区：
文献类型：
--
作者：
Joseph Davis;Niranjan S. Kulkarni;Jinghua Yang;A. Dengi;S. Vrudhula
本文提出了一种完全隐藏数字标准单元功能的方法。这是通过差分阈值逻辑门（TLG）实现的。具有n个输入的TLG实现了n个变量的布尔函数的一个子集，这些函数是线性阈值函数。当且仅当输入的整数加权线性算术和等于或超过给定的整数阈值时，这种门的输出为1。我们提出了一种TLG的新颖架构，它不仅允许单个TLG实现大量复杂的逻辑功能（使用传统逻辑原语实现时需要多级逻辑），而且还允许通过给输入晶体管分配晶体管阈值电压来选择该函数子集。为了混淆TLG的功能，通过将一些输入的器件阈值设置为高Vt，将它们的权重设置为零。其余晶体管的阈值电压设置为低Vt以增加它们的跨导。其栅极由给定输入xi驱动的低Vt晶体管的数量决定了该输入的权重。TLG的功能不是由单元本身决定的，而是由连接到其输入的信号决定的。这使得通过从函数的支撑集中实质上移除一些变量来隐藏函数的支撑集成为可能。这是通过对输入晶体管选择性地分配高Vt和低Vt来实现的。我们描述了如何将TLG的标准单元库与传统标准单元混合以实现复杂的逻辑电路，其功能永远无法通过逆向工程发现。在ST 65nm工艺上合成了一个32位华莱士树乘法器和一个28位4抽头滤波器，进行了布局布线，然后在有和没有混淆的情况下进行了包括提取寄生参数的模拟。通过混淆单元，在单元级别上延迟显示增加了约5%。在相同频率下运行时，两个混淆设计的面积（25%）和动态功耗（30%）都比其未混淆的CMOS对应设计低得多。
This paper proposes a method to completely hide the functionality of a digital standard cell. This is accomplished by a differential threshold logic gate (TLG). A TLG with n inputs implements a subset of Boolean functions of n variables that are linear threshold functions. The output of such a gate is one if and only if an integer weighted linear arithmetic sum of the inputs equals or exceeds a given integer threshold. We present a novel architecture of a TLG that not only allows a single TLG to implement a large number of complex logic functions, which would require multiple levels of logic when implemented using conventional logic primitives, but also allows the selection of that subset of functions by assignment of the transistor threshold voltages to the input transistors. To obfuscate the functionality of the TLG, weights of some inputs are set to zero by setting their device threshold to be a high Vt. The threshold voltage of the remaining transistors is set to low Vt to increase their transconductance. The number of low Vt transistors whose gates are driven by a given input xi determines the weight of that input. The function of a TLG is not determined by the cell itself but rather the signals that are connected to its inputs. This makes it possible to hide the support set of the function by essentially removing some variable from the support set of the function. This is done by selective assignment of high and low Vt to the input transistors. We describe how a standard cell library of TLGs can be mixed with conventional standard cells to realize complex logic circuits, whose function can never be discovered by reverse engineering. A 32-bit Wallace tree multiplier and a 28-bit 4-tap filter were synthesized on an ST 65nm process, placed and routed, then simulated including extracted parastics with and without obfuscation. By obfuscating the cells the delay was shown to increase by approximately 5% at the cell level. Both obfuscated designs had much lower area (25%) lower area and much lower dynamic power (30%) than their nonobfuscated CMOS counterparts, operating at the same frequency.