Tolerating Defects in Low-Power Neural Network Accelerators Via Retraining-Free Weight Approximation
Tolerating Defects in Low-Power Neural Network Accelerators Via Retraining-Free Weight Approximation
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DOI：
10.1145/3477016
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发表时间：
2021-09
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影响因子：
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通讯作者：
Fateme S. Hosseini;Fanruo Meng;Chengmo Yang;Wujie Wen;Rosario Cammarota
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作者：
Fateme S. Hosseini;Fanruo Meng;Chengmo Yang;Wujie Wen;Rosario Cammarota
硬件加速器对于在资源受限的嵌入式设备上适应不断增加的深度神经网络（DNN）工作负载至关重要。虽然加速器促进了快速和节能的DNN操作，但它们的准确性受到片上和片外存储器中故障的威胁，其中存储着数百万个DNN权重。新兴的非易失性存储器（NVM）的使用进一步使DNN加速器暴露于由于不成熟的制造、有限的耐久性和老化而导致的不可忽略的永久性缺陷率。为了容忍基于NVM的DNN加速器中的缺陷，以前的工作要么需要额外的硬件冗余，要么执行缺陷感知的再训练，从而带来显著的开销。相比之下，本文提出了一套算法，利用设置的灵活性，在重量记忆中的无故障位有效地近似权重值，以减轻缺陷引起的准确性下降。这些算法可以作为一个一步的解决方案时，加载的权重嵌入式设备。它们只需要微不足道的硬件支持，并施加可以忽略不计的运行时开销。在流行的DNN模型上的实验表明，即使在权重记忆中的缺陷率升高的情况下，所提出的技术也成功地提高了推理精度。
Hardware accelerators are essential to the accommodation of ever-increasing Deep Neural Network (DNN) workloads on the resource-constrained embedded devices. While accelerators facilitate fast and energy-efficient DNN operations, their accuracy is threatened by faults in their on-chip and off-chip memories, where millions of DNN weights are held. The use of emerging Non-Volatile Memories (NVM) further exposes DNN accelerators to a non-negligible rate of permanent defects due to immature fabrication, limited endurance, and aging. To tolerate defects in NVM-based DNN accelerators, previous work either requires extra redundancy in hardware or performs defect-aware retraining, imposing significant overhead. In comparison, this paper proposes a set of algorithms that exploit the flexibility in setting the fault-free bits in weight memory to effectively approximate weight values, so as to mitigate defect-induced accuracy drop. These algorithms can be applied as a one-step solution when loading the weights to embedded devices. They only require trivial hardware support and impose negligible run-time overhead. Experiments on popular DNN models show that the proposed techniques successfully boost inference accuracy even in the face of elevated defect rates in the weight memory.