The Magic Rule of Tiles: Virtual Delay Insensitivity
The Magic Rule of Tiles: Virtual Delay Insensitivity
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Tiles 的神奇规则：虚拟延迟不敏感
DOI：
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
A. Yakovlev
中科院分区：
文献类型：
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作者：
D. Shang;Fei Xia;Stanislavs Golubcovs;A. Yakovlev
延迟不敏感是一种理论上有吸引力的设计原则，它有助于电路抵抗工艺变化，特别是在系统级将其表现为延迟变化。不幸的是，延迟不敏感（DI）设计对于大多数实际系统来说是不切实际的。速度无关（SI）设计在实践中经常被用作次佳方法。与当前和未来技术节点的逻辑门相比，布线的扩展变得越来越困难，SI 系统作为 DI 系统的“近似值”越来越不被接受。本文提出了一种基于将复杂系统分解为简单、可管理的块的方法，这些块可以以 SI 方式安全地呈现。然后使用满足 DI 要求的互连来连接这些块，以在系统级别获得“虚拟 DI”行为。我们通过基于图块的多路访问仲裁器实现来演示这种方法。
Delay-insensitivity is a theoretically attractive design principle which helps circuits to be resistant to process variations, particularly exhibiting them selves at the system level as delay variations. Unfortunately, delay insensitive (DI) design is impractical for most real systems. Speed independent (SI) design is often used in practice as a next best approach. With the scaling of wires becom ing more and more difficult compared with logic gates at current and future technology nodes, SI systems are becoming less acceptable as “approximates” for DI systems. This paper proposes an approach based on decomposing complex systems into simple, manageable blocks which can be safely rendered in an SI manner. These blocks are then connected using interconnects which satisfy DI requirements to obtain “virtual DI” behaviour at system level. We demonstrate this approach with a tile-based implementation of a multi-access arbiter.