A single ended 6T SRAM cell design for ultra-low-voltage applications
A single ended 6T SRAM cell design for ultra-low-voltage applications
复制标题
适用于超低电压应用的单端 6T SRAM 单元设计
DOI：
--
复制
发表时间：
2008
影响因子：
0.8
通讯作者：
S. Mohanty
中科院分区：
文献类型：
--
作者：
Jawar Singh;D. Pradhan;S. Hollis;S. Mohanty
In this paper, we present a novel six-transistor (6T) single-ended static random access memory (SE-SRAM) cell for ultralow-voltage applications. The proposed design has a strong 2.65X worst case read static noise margin (SNM) compared to a standard 6T SRAM. A strong write-ability of logic ‘one’ is achieved, which is problematic in an SE-SRAM cell with a 36% improvement compared to standard 6T SRAMs. A 16 × 16 × 32 bit SRAM with proposed and standard 6T bitcells is simulated and evaluated for read SNM, write-ability and power. The dynamic and leakage power dissipation in the proposed 6T SRAM are reduced by 28% and 21%, respectively, as compared to standard 6T SRAM.
