Rigorous Stability Criterion for Digital Phase Locked Loops
Rigorous Stability Criterion for Digital Phase Locked Loops
复制标题
数字锁相环的严格稳定性标准
DOI：
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复制
发表时间：
2008
期刊：
影响因子：
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通讯作者：
R. Farrell
中科院分区：
文献类型：
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作者：
B. Daniels;R. Farrell
本文提出了严格的稳定性准则
用于任意阶数字锁相环 (DPLL)，带有电荷泵鉴频鉴相器 (CP-PFD)
组件。此类系统的稳定性边界是
使用分段线性方法对 CP-PFD 组件块的非线性特性进行建模来确定。型号
在预定数量的输入参考信号采样周期之后，将控制电压计算为小的初始电压偏移。本文特别深入研究了二阶系统。由所提出的技术定义的二阶稳定性边界与现有线性理论稳定性边界相比，显示出显着的改进。提出了使用数值迭代解决方案所提出的技术对高阶系统的适用性。最后，所提出的方法用于确定三阶系统的稳定性边界，从而确定稳定系统的分量值。使用这些元件值，使用电路级仿真来仿真 DPLL 对初始控制电压偏移的响应。
索引术语—高阶、锁相环、分段
线性、稳定。
This paper proposes a rigorous stability criterion
for an arbitrary order digital phase locked loop (DPLL), with a charge pump phase frequency detector (CP-PFD)
component. Stability boundaries for such systems are
determined using piecewise linear methods to model the nonlinear nature of the CP-PFD component block. The model
calculates the control voltage, after a predetermined number of input reference signal sampling periods, to a small initial voltage offset. This paper, in particular, takes an in-depth look at the second order system. The second order stability boundaries, as defined by the proposed technique, are compared to that of existing linear theory stability boundaries, and display a significant improvement. The applicability of the proposed technique to higher order systems, using a numerically iterative solution, is presented. Finally the proposed methodology is used to determine the stability boundary of a third order system and thus the component values for a stable system. Using these component values the response of the DPLL to an initial control voltage offset is simulated using a circuit level simulation.
Index Terms—High Order, Phase Locked Loop, Piecewise
Linear, Stability.