On testing the path delay faults of a microprocessor using its instruction set
On testing the path delay faults of a microprocessor using its instruction set
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利用指令集测试微处理器的路径延迟故障
DOI：
10.1109/vtest.2000.843821
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发表时间：
2000
期刊：
影响因子：
--
通讯作者：
K. Cheng
中科院分区：
文献类型：
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作者：
Wei;Angela Krstic;K. Cheng
本文讨论了使用指令测试微处理器中的路径延迟故障的问题。可以观察到，微处理器中的结构上可测试的路径(即，通过全速扫描可测试的路径)可能不能通过其指令来测试，这仅仅是因为没有指令序列能够产生所需的测试序列，该测试序列可以敏化路径并将故障效应捕获到高速目标输出/触发器中。这些路径称为功能无法测试的路径。我们讨论了功能不可测路径上的延迟缺陷对整体电路性能的影响，并说明如果延迟缺陷不会导致路径延迟超过时钟周期的两倍，则不需要对其进行测试。此类路径的识别有助于确定可实现的路径延迟故障复盖率，并减少后续测试生成工作。在两个微处理器(Parwan和DLX)上的实验结果表明，相当大比例的结构可测试路径在功能上是不可测试的，因此不需要测试。
This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable through at-speed scan) in a microprocessor might not be testable by its instructions simply because no instruction sequence can produce the desired test sequence which can sensitize the paths and capture the fault effect into the destination output/flip-flop at-speed. These paths are called functionally untestable paths. We discuss the impact of delay defects on the functionally untestable paths on the overall circuit performance and illustrate that they do not need to be tested if the delay defect does not cause the path delay to exceed twice the clock period. Identification of such paths helps determine the achievable path delay fault coverage and reduce the subsequent test generation effort. The experimental results for two microprocessors (Parwan and DLX) indicate that a significant percentage of structurally testable paths are functionally untestable and thus need not be tested.