ELP2IM: Efficient and Low Power Bitwise Operation Processing in DRAM
ELP2IM: Efficient and Low Power Bitwise Operation Processing in DRAM
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DOI：
10.1109/hpca47549.2020.00033
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发表时间：
2020-02
期刊：
影响因子：
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通讯作者：
Xin Xin-Xin;Youtao Zhang;Jun Yang
中科院分区：
文献类型：
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作者：
Xin Xin-Xin;Youtao Zhang;Jun Yang
最近提出的基于动态随机存取存储器（DRAM）的以内存为中心的架构在应对现代计算系统的内存墙挑战方面展现出了巨大潜力。这类架构利用多行的电荷共享来实现内存中的按位运算。然而，现有的设计在很大程度上依赖预留行来进行计算，这导致了较高的数据移动开销、较大的运算延迟、较高的能耗以及较低的运算可靠性。在本文中，我们提出了ELP2IM，一种高效且低功耗的内存中处理架构，以解决上述问题。ELP2IM利用DRAM子阵列中读出放大器的两种稳定状态，从而能够有效减少子阵列内数据移动的次数以及同时打开的DRAM行的数量，相比现有设计在性能和能耗方面具有很大优势。我们的实验结果表明，在实际应用中，ELP2IM的能效比最先进的基于DRAM的以内存为中心的设计提高了两倍多。
Recently proposed DRAM based memory-centric architectures have demonstrated their great potentials in addressing the memory wall challenge of modern computing systems. Such architectures exploit charge sharing of multiple rows to enable in-memory bitwise operations. However, existing designs rely heavily on reserved rows to implement computation, which introduces high data movement overhead, large operation latency, large energy consumption, and low operation reliability. In this paper, we propose ELP2IM, an efficient and low power processing in-memory architecture, to address the above issues. ELP2IM utilizes two stable states of sense amplifiers in DRAM subarrays so that it can effectively reduce the number of intra-subarray data movements as well as the number of concurrently opened DRAM rows, which exhibits great performance and energy consumption advantages over existing designs. Our experimental results show that the power efficiency of ELP2IM is more than 2X improvement over the state-of-the-art DRAM based memory-centric designs in real application.