Adiabatic Logic: Future Trend and System Level Perspective
Adiabatic Logic: Future Trend and System Level Perspective
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发表时间：
2011-11
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通讯作者：
P. Teichmann
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作者：
P. Teichmann
在超低功耗方面，绝热逻辑是静态 CMOS 电路设计的潜在继承者。未来的发展，如最小特征尺寸的不断缩小以及革命性的新颖晶体管概念，将改变绝热逻辑所获得的门级节省。此外，在绝热电路的设计中必须考虑退化效应恶化的影响。研究了技术趋势对绝热逻辑品质因数、节能潜力和最佳工作频率的影响，以及退化相关问题。绝热逻辑受益于未来器件，不易受到热载流子注入的影响，并且与静态 CMOS 电路相比，偏置温度不稳定性的影响更小。主要兴趣还在于所应用的电源时钟信号的有效生成。该振荡电源可通过断开电路在短空闲时间内节省能源。生成电源时钟的有效方法是使用同步 2N2P LC 振荡器，该振荡器对于图案引起的电容变化也具有鲁棒性。通过门控同步信号提出了一种易于实现但功能强大的电源时钟门控补充。介绍了关闭系统的多种实施方式，并对其适用性以及节能能力和数据保留等其他方面进行了评级。绝热逻辑的有利使用需要紧凑且高效的算术结构。根据能耗和面积使用对各种加法器结构和坐标旋转数字计算机进行比较和评级，由此产生的相对于静态 CMOS 的节能潜力证明了绝热逻辑的超低功耗能力。最后，新的电路拓扑还必须在生产率方面与静态 CMOS 竞争。在 130nm 测试芯片上，包含 FIR 滤波器的大规模测试工具以绝热逻辑实现，利用标准的、基于库的设计流程，进行制造、测量并与静态 CMOS 对应物的模拟进行比较，测量的节省因子符合模拟获得的值。由此得出的结论是，由于绝热逻辑不仅与 CMOS 技术兼容，而且还与为静态 CMOS 系统设计开发的电子设计自动化 (EDA) 工具兼容，因此可以进行高效设计。
Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the power-clock is by means of the synchronous 2N2P LC oscillator, which is also robust with respect to pattern-induced capacitive variations. An easy to implement but powerful power-clock gating supplement is proposed by gating the synchronization signals. Diverse implementations to shut down the system are presented and rated for their applicability and other aspects like energy reduction capability and data retention. Advantageous usage of adiabatic logic requires compact and efficient arithmetic structures. A broad variety of adder structures and a Coordinate Rotation Digital Computer are compared and rated according to energy consumption and area usage, and the resulting energy saving potential against static CMOS proves the ultra-low-power capability of adiabatic logic. In the end, a new circuit topology has to compete with static CMOS also in productivity. On a 130nm test chip, a large scale test vehicle containing an FIR filter was implemented in adiabatic logic, utilizing a standard, library-based design flow, fabricated, measured and compared to simulations of a static CMOS counterpart, with measured saving factors compliant to the values gained by simulation. This leads to the conclusion that adiabatic logic is ready for productive design due to compatibility not only to CMOS technology, but also to electronic design automation (EDA) tools developed for static CMOS system design.