Impact of interface layer on charge trapping in Si:HfO2 based FeFET
Impact of interface layer on charge trapping in Si:HfO2 based FeFET
复制标题
界面层对 Si:HfO2 基 FeFET 电荷俘获的影响
DOI:
10.1109/iirw49815.2020.9312866
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发表时间:
2020
期刊:
影响因子:
--
通讯作者:
J. V. Houdt
中科院分区:
文献类型:
--
作者:
T. Jung;B. O’Sullivan;N. Ronchi;D. Linten;C. Shin;J. V. Houdt
The impact of interface layer on charge trapping and polarization switching at multiple temperatures is investigated. At high temperature, the FeFET with metal-ferroelectric-insulator semiconductor (MFIS) gate-stack shows conventional electron-trapping dominated PBTI (i.e. $\Delta \mathrm{V}_{\mathrm{t}}\lt0$), whereas at room temperature, negative threshold voltage shifts $(\Delta \mathrm{V}_{\mathrm{t}})$ are observed. We demonstrate a link between interface layer and the subsequently-deposited ferroelectric layers effective permittivity: higher permittivity, consistent with higher tetragonal phase/ lower orthorhombic phase content is seen when the ferroelectric layer is deposited on hydrogen terminated silicon, whereas anomalous BTI consistent with higher orthorhombic phase is observed when the ferroelectric is deposited on oxygen-rich $(\mathrm{S}\mathrm{i}\mathrm{O}_{2}$, SiON) surfaces.