Impact of interface layer on charge trapping in Si:HfO2 based FeFET

Impact of interface layer on charge trapping in Si:HfO2 based FeFET
复制标题

界面层对 Si:HfO2 基 FeFET 电荷俘获的影响

DOI:
10.1109/iirw49815.2020.9312866
复制
发表时间:
2020
期刊:
2020 IEEE International Integrated Reliability Workshop (IIRW)
影响因子:
--
通讯作者:
J. V. Houdt
J. V. Houdt
中科院分区:
--
文献类型:
--
作者:
T. Jung;B. O’Sullivan;N. Ronchi;D. Linten;C. Shin;J. V. Houdt

文献摘要

被引文献

相似文献

研究了不同温度下界面层对电荷俘获和极化反转的影响。在高温下,采用金属-铁电-绝缘体半导体(MFIS)栅叠层的FeFET表现出传统的电子俘获主导的PBTI(即$\Delta \mathrm{V}_{\mathrm{t}}\lt 0 $),而在室温下,观察到负阈值电压漂移$(\Delta \mathrm{V}_{\mathrm{t}})$。我们证明了界面层和间接沉积的铁电层有效介电常数之间的联系:当铁电层沉积在氢终止的硅上时,可以看到与较高的四方相/较低的正交相含量一致的较高的介电常数,而当铁电体沉积在富氧的$上时,观察到与更高的正交相一致的反常BTI。(\mathrm{S}\mathrm{i}\mathrm{O}_{2}$,锡永)表面。
The impact of interface layer on charge trapping and polarization switching at multiple temperatures is investigated. At high temperature, the FeFET with metal-ferroelectric-insulator semiconductor (MFIS) gate-stack shows conventional electron-trapping dominated PBTI (i.e. $\Delta \mathrm{V}_{\mathrm{t}}\lt0$), whereas at room temperature, negative threshold voltage shifts $(\Delta \mathrm{V}_{\mathrm{t}})$ are observed. We demonstrate a link between interface layer and the subsequently-deposited ferroelectric layers effective permittivity: higher permittivity, consistent with higher tetragonal phase/ lower orthorhombic phase content is seen when the ferroelectric layer is deposited on hydrogen terminated silicon, whereas anomalous BTI consistent with higher orthorhombic phase is observed when the ferroelectric is deposited on oxygen-rich $(\mathrm{S}\mathrm{i}\mathrm{O}_{2}$, SiON) surfaces.