Study and integration of a parametric neighbouring interconnection network in a massively parallel architecture on FPGA
Study and integration of a parametric neighbouring interconnection network in a massively parallel architecture on FPGA
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FPGA 大规模并行架构中参数化相邻互连网络的研究和集成
DOI：
10.1109/aiccsa.2009.5069350
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
J. Dekeyser
中科院分区：
文献类型：
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作者：
M. Baklouti;M. Abid;P. Marquet;J. Dekeyser
由于其面积和能源效率，单指令多数据处理器越来越多地用于多媒体应用的嵌入式系统。处理元件之间的相邻通信是 SIMD 处理器中的一个关键问题。它们存在于大多数数据并行应用程序中。然而，主要并行架构缺乏灵活性是其主要缺点。为了提高大规模并行架构的性能，特别是在相邻通信方面，我们需要一个灵活的参数化通信网络。本文重点讨论片上系统 (SoC) 中 SIMD 架构中参数化最近邻互连网络的设计问题。该网络可以配置为多种拓扑，使其灵活且参数化，以满足不同的应用需求。所提出的架构根据面积（成本）和性能（执行时间）进行评估，分别从综合和仿真结果中推导出来。实验是在具有不同拓扑的不同架构上进行的。为了评估所提出的架构的性能，最终实现了 FIR 应用程序。
Single Instruction Multiple Data processors are increasingly used in embedded systems for multimedia applications because of their area and energy-efficiency. Neighboring communications between the processing elements are a key issue in SIMD processors. They are present in most data parallel applications. However, the lack of flexibility in major parallel architectures is its main shortcoming. In order to improve the performances of a massively parallel architecture, especially in term of neighboring communication we need a flexible and parametric communication network. This paper focuses on the problems with the design of a parametric nearest neighborhood interconnection network in a SIMD architecture in System on Chip (SoC). This network can be configured in multiple topologies making it flexible and parametric in order to suit different application needs. The proposed architecture is evaluated in terms of area (cost) and performance (execution time), which are deduced respectively from synthesis and simulation results. Experiments are performed on different architectures with various topologies. In order to evaluate the performance of the proposed architecture, a FIR application is finally implemented.