Silicon nanocrystals: from Coulomb blockade to memory arrays
Silicon nanocrystals: from Coulomb blockade to memory arrays
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DOI：
10.1109/nano.2004.1392328
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发表时间：
2004-08
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影响因子：
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通讯作者：
R. Steimle;R. Rao;M. Sadd;C. Swift;B. Hradsky;S. Straub;T. Merchant;M. Stoker;C. Parikh;S. Anderson;M. Rossow;J. Yater;B. Acred;K. Harber;E. Prinz;B. White;R. Muralidhar
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文献类型：
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作者：
R. Steimle;R. Rao;M. Sadd;C. Swift;B. Hradsky;S. Straub;T. Merchant;M. Stoker;C. Parikh;S. Anderson;M. Rossow;J. Yater;B. Acred;K. Harber;E. Prinz;B. White;R. Muralidhar
硅纳米晶体通过增加对经由隧道氧化物缺陷的电荷损失的免疫力来提供解决常规闪存的隧道氧化物缩放的挑战性问题的机会。硅微电子存储器技术中的新方面包括库仑阻塞或电荷限制效应、原子成核和在后续处理和编程/擦除耐久性特性期间保护它们的微电子钝化。本文讨论了上述特点，并最终提出了显着的结果，从4 Mb NOR存储器阵列采用90 nm CMOS工艺制造。使用5 nm的隧道氧化物厚度和6 V电源获得包括紧密Vt分布的优异存储器特性。
Silicon nanocrystals provide opportunity to solve the challenging problem of tunnel oxide scaling of conventional flash memories by increasing immunity to charge loss via tunnel oxide defects. New aspects in silicon nanocrystal memory technology include Coulomb blockade or charge confinement effects, atomistic nucleation, and nanocrystal passivation to preserve them during subsequent processing and program/erase endurance characteristics. This paper discusses the above characteristics and culminates in presenting salient results from 4 Mb NOR memory arrays fabricated using 90 nm CMOS technology. Excellent memory characteristics including tight Vt distributions are obtained using a tunnel oxide thickness of 5 nm and a 6 V power supply.