Vertical GaN power FET on bulk GaN substrate

Vertical GaN power FET on bulk GaN substrate
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块状 GaN 衬底上的垂直 GaN 功率 FET

DOI:
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发表时间:
2016
期刊:
Device Research Conference
影响因子:
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通讯作者:
T. Palacios
T. Palacios
中科院分区:
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文献类型:
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作者:
Min;M. Pan;Xiang Gao;T. Palacios

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在硅衬底上工作电压低于650 V的横向GaN晶体管目前已商品化。这种横向几何结构的主要缺点是晶体管面积(因此,它的成本)与击穿电压成正比。此外,许多材料界面暴露在高电场中,这降低了可靠性并防止雪崩击穿。对于高电压、大电流的应用,横向器件的尺寸会急剧增加,而且很难在一个表面上处理非常高的电流水平。由于电场峰值在远离表面的地方,预计垂直器件将减小模具尺寸,并且更加可靠。目前研究最多的垂直GaN晶体管——孔径垂直电子晶体管(CAVET)在性能上已经取得了显著的进步,但它仍然面临着两个挑战。首先,CAVET结构需要在n掺杂GaN层中埋入p掺杂电流阻断层。充分激活氮化镓中的p掺杂剂Mg是非常具有挑战性的,并且垂直泄漏电流趋于高。其次,对AlGaN/GaN接入区域的高质量再生的需求大大增加了制造成本。在这项工作中,已经开发了一种新型的垂直FET (VFET)结构在大块GaN衬底上,以解决传统功率垂直GaN晶体管的挑战(图1)。这种VFET结构不需要掺p的GaN阻流层或材料再生。演示了一种阈值电压为0.5 V、通断电流比为1011的GaN VFET。
Lateral GaN transistors on Si substrates operating at voltage below 650 V are commercially available today. The main drawback of this lateral geometry is that the transistor area (and, therefore, its cost) is proportional to the breakdown voltage. In addition, numerous material interfaces are exposed to high electric fields, which reduces reliability and prevents avalanche breakdown. For higher-voltage high-current applications, the lateral-device size increases dramatically, and very high current levels are difficult to handle on just one surface. It is expected that vertical devices would reduce the die size and be more reliable as the electric field peaks far away from the surface. The most studied vertical GaN transistor, the current aperture vertical electron transistor (CAVET), has made significant progress in performance, but it still faces two challenges [1]. First, the CAVET structure requires a p-doped current blocking layer buried in the n-doped GaN layer. Fully activating the p-dopant Mg in GaN has been found very challenging and the vertical leakage current tends to be high. Second, the needs for a high quality regrowth of the AlGaN/GaN access region substantially increases the manufacturing cost. In this work, a novel vertical FET (VFET) structure on bulk GaN substrate has been developed to address the challenges of conventional power vertical GaN transistors (Fig. 1). This VFET structure does not require a p-doped GaN current-blocking layer or material regrowth. A GaN VFET with 0.5 V threshold voltage and 1011 on/off current ratio was demonstrated.