Model for Delay Faults Based upon Paths
Model for Delay Faults Based upon Paths
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发表时间：
1985
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通讯作者：
Gordon L. Smith
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作者：
Gordon L. Smith
分析了在时钟环境中组合逻辑的延迟测试。引入了基于路径的模型以进行延迟故障。总延迟超过时钟间隔的任何路径称为“路径故障”。这是一个全局延迟故障模型，因为它与整个路径相关联。另一方面，更熟悉的缓慢升高或慢速门延迟故障是局部故障模型。描述了一个过程，该过程标识了通过一组模式测试路径故障的路径。它不涉及延迟模拟。如此确定的路径对路径故障进行了测试，而与网络的任何单个门的延迟无关。
Delay testing of combinational logic in a clocked environment is analyzed. A model based upon paths is introduced for delay faults. Any path with a total delay exceeding the clock interval is called a "path fault." This is a global delay fault model because it is associated with an entire path. The more familiar slow-to-rise or slow-to-fall gate delay fault, on the other hand, is a local fault model. A procedure is described which identifies paths which are tested for path faults by a set of patterns. It does not involve delay simulation. The paths so identified are tested for path faults independent of the delays of any individual gate of the network.