Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory
Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory
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DOI：
10.1147/jrd.2017.2716579
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发表时间：
2017-07
期刊：
影响因子：
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通讯作者：
P. Narayanan;Alessandro Fumarola;Lucas L. Sanches;K. Hosokawa;S. Lewis;R. Shelby;G. Burr
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文献类型：
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作者：
P. Narayanan;Alessandro Fumarola;Lucas L. Sanches;K. Hosokawa;S. Lewis;R. Shelby;G. Burr
通过在数据的位置执行计算，非VON NEUMANN（VN）计算应为以数据为中心的工作负载（例如基于VN）的方法（例如，基于VN）的方法（例如，对深度学习）提供了速度和速度好处。使用基于非易失性记忆（NVM）突触的大规模深神经网络，成功将需要与常规方法目的地竞争的性能水平（例如，深神经网络分类精度）此类NVM设备的固有缺陷，还需要大量平行但低功率的读写访问权限，我们将重点介绍以后的要求，并概述了工程折衷方案，以执行并行读取和写入大型NVM设备为了通过本地的模拟计算实现此加速度。与传统记忆应用中发现的众所周知的要求有很大不同。
By performing computation at the location of data, non-Von Neumann (VN) computing should provide power and speed benefits over conventional (e.g., VN-based) approaches to data-centric workloads such as deep learning. For the on-chip training of large-scale deep neural networks using nonvolatile memory (NVM) based synapses, success will require performance levels (e.g., deep neural network classification accuracies) that are competitive with conventional approaches despite the inherent imperfections of such NVM devices, and will also require massively parallel yet low-power read and write access. In this paper, we focus on the latter requirement, and outline the engineering tradeoffs in performing parallel reads and writes to large arrays of NVM devices to implement this acceleration through what is, at least locally, analog computing. We address how the circuit requirements for this new neuromorphic computing approach are somewhat reminiscent of, yet significantly different from, the well-known requirements found in conventional memory applications. We discuss tradeoffs that can influence both the effective acceleration factor (“speed”) and power requirements of such on-chip learning accelerators.