Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part II: Implications for Process, Device, and Circuit Design

Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part II: Implications for Process, Device, and Circuit Design
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DOI:
10.1109/ted.2010.2063270
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发表时间:
2010-09
影响因子:
3.1
通讯作者:
H. Dadgour;K. Endo;V. De;K. Banerjee
H. Dadgour;K. Endo;V. De;K. Banerjee
中科院分区:
工程技术2区
文献类型:
--
作者:
H. Dadgour;K. Endo;V. De;K. Banerjee

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本文研究了高 k/金属栅极器件中晶粒取向引起的功函数变化 (WFV) 对工艺、器件和电路设计的影响。 WFV 是由金属晶粒的功函数对其方向的依赖性引起的,并在配套论文(第一部分)中进行了分析建模。本文使用该建模框架研究了 WFV 的各种含义。结果表明,工艺设计人员可以利用所提出的模型,通过识别适当的材料和制造工艺来减少 WFV 的影响。例如,研究了四种类型的金属氮化物栅极材料(NMOS器件的TiN和TaN以及PMOS器件的WN和MoN),结果表明TiN和WN导致较低的V_th波动。此外,器件工程师可以使用这些分析模型来研究 WFV 对各种类型的经典和非经典金属栅极 CMOS 晶体管的影响。举例来说,结果表明,对于给定的沟道长度,与全耗尽型 SOI 和体硅器件相比,单鳍 FinFET 由于栅极面积较大,受 WFV 的影响较小。此外,电路设计人员可以受益于所提出的建模框架,该框架允许在此类 V_th 波动下直接评估电路的关键性能和可靠性参数。例如,在存在 WFV 导致的 V_th 波动的情况下对 SRAM 单元进行了分析,结果表明这种变化会导致相当大的性能和可靠性下降。
This paper investigates the process, device, and circuit design implications of grain-orientation-induced work function variation (WFV) in high-k/metal-gate devices. WFV is caused by the dependence of the work function of metal grains on their orientations and is analytically modeled in the companion paper (part I). Using this modeling framework, various implications of WFV are investigated in this paper. It is shown that process designers can utilize the proposed models to reduce the impact of WFV by identifying proper materials and fabrication processes. For instance, four types of metal nitride gate materials (TiN and TaN for NMOS devices and WN and MoN for PMOS devices) are studied, and it is shown that TiN and WN result in lower V_th fluctuations. Moreover, device engineers can study the impact of WFV on various types of classical and nonclassical metal-gate CMOS transistors using these analytical models. As an example, it is shown that, for a given channel length, single-fin FinFETs are less affected by WFV compared to fully depleted SOI and bulk-Si devices due to their larger gate area. Furthermore, circuit designers can benefit from the proposed modeling framework that allows straightforward evaluation of the key performance and reliability parameters of the circuits under such V_th fluctuations. For instance, an SRAM cell is analyzed in the presence of V_th fluctuations due to WFV, and it is shown that such variations can result in considerable performance and reliability degradation.