Fabrication of Planar-Integrated SIS Mixer Circuits with Improved Uniformity and Yield
Fabrication of Planar-Integrated SIS Mixer Circuits with Improved Uniformity and Yield
复制标题
DOI：
10.1007/s10909-020-02433-2
复制
发表时间：
2020-03
影响因子：
2
通讯作者：
S. Ezaki;W. Shan;Y. Uzawa
中科院分区：
文献类型：
--
作者：
S. Ezaki;W. Shan;Y. Uzawa
研制了用于多波束外差接收机的单像素超导体-绝缘体-超导体(SIS)混频集成电路。我们引入了等离子体增强化学气相沉积(PE-CVD)用于绝缘层沉积，以及机器对准通孔刻蚀用于在SIS结上定义接触孔，以获得高的均匀性和成品率。在PE-CVD中，我们采用了压缩/拉伸/压缩SiO_2三层膜技术来控制薄膜的应力。SiO_2三层膜的应力很稳定，可以忽略不计。采用PE-CVD工艺和通孔刻蚀工艺，提高了单像素原型SIS混频集成电路的均匀性和结合率。
Single-pixel prototype superconductor–insulator–superconductor (SIS) mixer integrated circuits (ICs) for multi-beam heterodyne receivers were fabricated. We introduced plasma-enhanced chemical vapor deposition (PE-CVD) for insulator layer deposition and machine-aligned via-hole etching for contact-hole definition on SIS junctions to achieve high uniformity and yield. In the PE-CVD, we applied a compressive/tensile/compressive SiO2trilayer technique to control the film stress. The SiO2trilayer stress was stable and negligibly low. The uniformity and junction quality yield of the single-pixel prototype SIS mixer ICs were improved in the process applying the PE-CVD and the via-hole etching.