High-performance architectures for elementary function generation
High-performance architectures for elementary function generation
复制标题
用于生成初等函数的高性能架构
DOI：
10.1109/arith.2001.930113
复制
发表时间：
2001
期刊：
影响因子：
--
通讯作者：
Jie Cheng
中科院分区：
文献类型：
--
作者：
Jun Cao;Belle W. Y. Wei;Jie Cheng
High-speed elementary function generation is crucial to the performance of many DSP applications. This paper presents three new architectures for generating elementary functions with IEEE single precision using second-order interpolation. These designs have been developed through a combination of architectural innovations and algorithm developments. They represent a range of trade-off between the use of memory modules and computational circuits. Our most memory intensive architecture uses one third less memory than alternative schemes while incurring no time penalty and minimal additional circuitry.
