A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS
A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS
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DOI：
10.1109/jssc.2008.917522
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发表时间：
2008-03
影响因子：
5.4
通讯作者：
G. Balamurugan;J. Kennedy;G. Banerjee;J. Jaussi;M. Mansuri;F. O’Mahony;B. Casper;R. Mooney
中科院分区：
文献类型：
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作者：
G. Balamurugan;J. Kennedy;G. Banerjee;J. Jaussi;M. Mansuri;F. O’Mahony;B. Casper;R. Mooney
我们提出了一个可扩展的低功耗I/O收发器在65 nm CMOS，能够在单板和背板FR 4通道5-15 Gbps的操作与功率效率之间的2.8-6.5 mW/Gbps。通过使用可扩展的收发器电路块以及电源电压、偏置电流和驱动器功率与数据速率的联合优化，实现了非线性功耗-性能折衷。低功耗操作通过电感链路端接的无源均衡、有源连续时间RX均衡、具有片上传输线的全局TX/RX时钟分配以及低噪声偏移校准接收器来实现。
We present a scalable low-power I/O transceiver in 65 nm CMOS, capable of 5-15 Gbps operation over single-board and backplane FR4 channels with power efficiencies between 2.8-6.5 mW/Gbps. Nonlinear power-performance tradeoff is achieved by the use of scalable transceiver circuit blocks and joint optimization of the supply voltage, bias currents and driver power with data rate. Low-power operation is enabled by passive equalization through inductive link termination, active continuous-time RX equalization, global TX/RX clock distribution with on-die transmission lines, and low-noise offset-calibrated receivers.