GaN vertical nanowire and fin power MISFETs
GaN vertical nanowire and fin power MISFETs
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GaN 垂直纳米线和鳍片功率 MISFET
DOI：
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
H. Xing
中科院分区：
文献类型：
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作者：
Zongyang Hu;Wenshen Li;K. Nomoto;M. Zhu;Xiang Gao;M. Pilla;D. Jena;H. Xing
GaN垂直功率器件在器件尺寸、可靠性和热管理等方面比横向器件具有许多优势。传统的功率晶体管采用p型口袋来实现E模式、RESURF和雪崩能力。然而，GaN垂直功率晶体管中的这种拓扑结构在实现[1]方面具有挑战性，因为难以在不影响击穿的情况下实现选择性区域掺杂：n型区域中的p型口袋，反之亦然。GaN UMOS-FET或沟槽MOSFET可以使用外延p层来实现，然而，在反型沟道中遭受低沟道迁移率[2，3]。仅使用n型GaN，可以实现具有吸引力的电流密度和击穿电压的耗尽模式垂直MISFET [4]。为了获得常关操作，鳍或纳米线（NW）柱是必要的几何形状。与鳍片相比，GaN纳米线具有额外的优点，包括上级静电控制和在异质衬底上低成本生长的可能性[5，6]。在这项工作中，我们报告了在体GaN衬底上首次实验演示NW-MISFET，并将其与在同一样本上制造的具有最先进性能的Fin-MISFET进行比较。纳米线MISFET中更好的静电栅极控制的好处是突出的。
GaN vertical power devices have many advantage over lateral device in device scaling, reliability and thermal management, etc. Traditional power transistors employ p-type pockets to achieve E-mode, RESURF and avalanche capabilities. However, this topology in GaN vertical power transistors has been challenging to implement [1] due to the difficulty to achieve selective area doping without compromising breakdown: p-type pockets in n-type regions or vice versa. The GaN UMOS-FETs or trench MOSFETs can be realized using epitaxial p-layers, however, suffer from low channel mobility in the inversion channel [2, 3]. Using n-type GaN only, depletion mode vertical MISFETs can be achieved with attractive current densities and breakdown voltages [4]. To get normally-off operation, Fin or nanowire (NW) pillars are necessary geometries. Compared with Fins, GaN nanowires have added advantages including superior electrostatic control and possibility for low-cost growth on foreign substrates [5, 6]. In this work, we report the first experimental demonstration of NW-MISFETs on bulk GaN substrates and compare them with Fin-MISFETs with the state-of-the-art performance fabricated on the same sample. The benefit of better electrostatic gate control in nanowire MISFETs are highlighted.