Power Supply Noise Analysis Methodology for DeepSubmicron VLSI Chip Design
Power Supply Noise Analysis Methodology for DeepSubmicron VLSI Chip Design
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DOI：
10.1109/9780470546413.ch30
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发表时间：
2002
期刊：
影响因子：
--
通讯作者：
Raminderpal Singh
中科院分区：
文献类型：
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作者：
Raminderpal Singh
本文描述了一种新的分析高性能微处理器片上电源噪声的设计方法。该方法基于集成的封装级和芯片级电源总线模型，以及每个功能块的模拟开关电路模型，为整个芯片提供了最完整和准确的Vdd分布分析。分析结果不仅同时为设计人员提供了感应性I噪声和阻性I R降数据，还使设计人员能够轻松识别芯片上的热点和芯片上的V。然后，可以进行全局和局部优化，如缓冲器大小调整、电源母线大小调整和片上去耦电容器放置，以最大化电路性能和最小化噪声。
This paper describes a new design methodology to analyze the on-chip power supply noise for high-performance microprocessors. Based on an integrated package-level and chip-level power bus model, and a simulated switching circuit model for each functional block, this methodology offers the most complete and accurate analysis of Vdd distribution for the entire chip. The analysis results not only provide designers with the inductive ?> I noise and the resistive I R drop data at the same time, but also allow designers to easily identify the hot spots on the chip and ?> V across the chip. global and local optimization such as buffer sizing, power bus sizing, and on-chip decoupling capacitor placement can then be conducted to maximize the circuit performance and minimize the noise.