An Ultra-high Speed Public Key Encryption Processor
An Ultra-high Speed Public Key Encryption Processor
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超高速公钥加密处理器
DOI：
10.1109/cicc.1992.591336
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发表时间：
1992
期刊：
影响因子：
--
通讯作者：
S. Davidson
中科院分区：
文献类型：
--
作者：
P. Ivey;S. Walker;J. Stern;S. Davidson
本文描述了一个实现512位RSA算法的公钥加密处理器的结构和设计。该芯片为6.2 × 4.2毫米，采用0.7微米CMOS、绝缘体上硅工艺设计，目标时钟速度为150MHz。它是一个独立的子系统，直接与标准微处理器接口，并能够以超过64k波特的速率加密（由于合同原因，我们目前无法透露emct的操作速度）。
This paper describes the architecture and design of a public key encryption processor which implements the RSA algorithm with key lengths of512 bits. The chip, which is 6.2 by 4.2 millimetres, has been designed in a 0.7 micron CMOS, silicon on insulator process and has a target clock speed of 15OMHz. It is a self contained subsystem which interfaces directly to standard microprocessors and will be capable of encrypting at rates well in excess of 64k baud (for contractural reasons we are unable, at this time, to disclose the emct speed of operation).