Industrially microfabricated ion trap with 1 eV trap depth
Industrially microfabricated ion trap with 1 eV trap depth
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DOI：
10.1088/2058-9565/ac7072
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发表时间：
2022-07-01
影响因子：
6.7
通讯作者：
Home, J.
中科院分区：
文献类型：
--
作者：
Auchter, S.;Axline, C.;Home, J.
扩展囚禁离子量子计算将需要在长时间内强大地捕获至少数百个离子，同时增加陷阱本身的复杂性和功能。对称的三维(3D)结构可以实现高陷阱深度，但微制造技术通常更适合于产生不太理想的陷阱条件的平面结构。我们提出了一种在堆叠的8英寸晶片上制造的离子陷阱，它是在大规模的微型机电系统微制造工艺中制造的，它提供了大体积的可重现的陷阱。电极被图案化在结合到间隔物上的两个相对晶片的表面上，形成在叠层上具有2.5µm对准标准偏差的3D结构。我们实现了一种设计，对于保持在200微米处的Ca-40(+)离子，从任一电极平面的陷阱深度为1 eV。我们对陷阱进行了表征，在0.6-3.8 MHz的模式频率范围内，实现了与模拟的+/-5%的测量一致性，并评估了跨多个陷阱位置的杂散电场。我们测量了在广泛的陷阱频率和温度范围内的运动加热率，在1 MHz和185K下观测到了40个声子/S。这种制备方法为产生新一代3D离子陷阱提供了一种高度可扩展的方法。
Scaling trapped-ion quantum computing will require robust trapping of at least hundreds of ions over long periods, while increasing the complexity and functionality of the trap itself. Symmetric three-dimensional (3D) structures enable high trap depth, but microfabrication techniques are generally better suited to planar structures that produce less ideal conditions for trapping. We present an ion trap fabricated on stacked eight-inch wafers in a large-scale micro-electro-mechanical system microfabrication process that provides reproducible traps at a large volume. Electrodes are patterned on the surfaces of two opposing wafers bonded to a spacer, forming a 3D structure with 2.5 mu m standard deviation in alignment across the stack. We implement a design achieving a trap depth of 1 eV for a Ca-40(+) ion held at 200 mu m from either electrode plane. We characterize traps, achieving measurement agreement with simulations to within +/- 5% for mode frequencies spanning 0.6-3.8 MHz, and evaluate stray electric field across multiple trapping sites. We measure motional heating rates over an extensive range of trap frequencies, and temperatures, observing 40 phonons/s at 1 MHz and 185 K. This fabrication method provides a highly scalable approach for producing a new generation of 3D ion traps.