Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices With Gate–Source/Drain Underlap
Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices With Gate–Source/Drain Underlap
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DOI：
10.1109/ted.2006.880369
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发表时间：
2006-08
影响因子：
3.1
通讯作者：
Seung-Hwan Kim;J. Fossum;Ji-Woon Yang
中科院分区：
文献类型：
--
作者：
Seung-Hwan Kim;J. Fossum;Ji-Woon Yang
Parasitic gate-source/drain (G-S/D) fringe capacitance in nonclassical nanoscale CMOS devices, e.g., double-gate (DG) MOSFETs, is shown, using two-dimensional numerical simulations, to be very significant, gate bias-dependent, and substantially reduced by a well-designed G-S/D underlap. Analytical modeling of the outer and inner components of the fringe capacitance is developed and verified by the numerical simulations; a BOX-fringe component is modeled for single-gate fully depleted silicon-on-insulator MOSFETs. With the new modeling implemented in UFDG, our process/physics-based generic compact model for DG MOSFETs, UFDG/Spice3 shows how nanoscale DG CMOS speed is severely affected by the fringe capacitance and how this effect can be moderated by an optimal underlap, which yields a good tradeoff between the parasitic capacitance and the S/D resistance
