Low-power fast (LPF) SRAM cell for write/read operation
Low-power fast (LPF) SRAM cell for write/read operation
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DOI：
10.1587/elex.8.1473
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
C. Prabhu;A. Singh
中科院分区：
文献类型：
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作者：
C. Prabhu;A. Singh
功耗和静态噪声容限（SNM）是存储器设计中最重要的参数。SRAM单元中功耗的主要来源是由于写入操作期间位线上的大电压摆幅。为了降低SRAM单元的功耗，提高SRAM单元的性能，我们提出了一种低功耗快速（LPF）SRAM单元。从功率、延迟和读取稳定性方面对单元进行了模拟。仿真结果表明，在1.2V（CMOS 0.12μm工艺）下，与6T存储单元相比，该存储单元的读写功耗分别降低了33%和57.12%。LPF单元的读取SNM是常规单元的2倍。
Power consumption and Static noise margin (SNM) are most important parameters for memory design. The main source of power consumption in SRAM cell is due to large voltage swing on the bitlines during write operation. To reduce the power consumption and enhance the performance of the SRAM cell, we propose a Low-power fast (LPF) SRAM cell. The cell is simulated in terms of power, delay and read stability. The simulated result shows that the read and write power of the proposed cell is reduced up to 33% and 57.12% at 1.2V (in CMOS 0.12µm technology) respectively compared to the 6T cell. The read SNM of the LPF cell is 2x times of the conventional cell.