Efficient 16 nm SRAM Design for FPGA’s
Efficient 16 nm SRAM Design for FPGA’s
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适用于 FPGA 的高效 16 nm SRAM 设计
DOI：
10.1109/spin.2018.8474069
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发表时间：
2018
期刊：
影响因子：
--
通讯作者：
Abdul Manan
中科院分区：
文献类型：
--
作者：
Abdul Manan
基于静态随机存取存储器（SRAM）的配置位用于将数据存储在查找表（LUTs）中，并使用SRAM内容完成通过开关矩阵的路由。日期写入操作仅在FPGA需要配置或重新配置时发生，因此功耗的主要来源来自空闲阶段的SRAM单元泄漏电流。低功耗SRAM单元设计在当今的fpga中形成了一个重要的要求，因为它是fpga中的关键部件之一，并且消耗了总功率的很大一部分。因此，提出了一种新颖的SRAM 6T结构，该结构仅在读写操作期间将单元电源提升到更高的VDD，在空闲阶段将电源线拉低到较低的电压。
Static Random Access Memories (SRAM) based configuration bits is used to store data in Look Up Tables (LUTs) and routing through switch matrix is accomplished using the SRAM contents. Date write operation takes place only when the FPGA needs to be configured or reconfigured and hence a major source of power consumption comes from the SRAM cell leakage current during idle phase. Low power SRAM cell design forms an important requirement in today’s FPGAs because it is one of the critical components in FPGAs and consumes a large fraction of the total power. Hence a novel SRAM 6T structure is proposed where cell power supply is raised to higher VDD only during read or write operation and supply line is pulled down to lower voltage during idle phase.