Single-Error Hardened and Multiple-Error Tolerant Guarded Dual Modular Redundancy Technique

Single-Error Hardened and Multiple-Error Tolerant Guarded Dual Modular Redundancy Technique
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单错误强化和多错误容错防护双模块冗余技术

DOI:
10.1109/vlsid.2018.71
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发表时间:
2018
期刊:
2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)
影响因子:
--
通讯作者:
Hemal Shah
Hemal Shah
中科院分区:
--
文献类型:
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作者:
Sai Aparna Aketi;Joycee Mekie;Hemal Shah

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为空间应用而设计的电路需要特别考虑耐受辐射。本文提出了一种单粒子瞬态(SET)的抗辐射加固设计(RHBD)技术--保护双模冗余(GDMR)。我们提出了一个简洁的数学程序,捕捉在任何给定的辐射硬设计(RHBD)技术的多个事件瞬变(MET)的影响。我们分析的有效性GDMR多事件瞬变(MET)对著名的三模冗余(TMR)techniqueusing该程序。我们的研究结果表明,GDMR逻辑门比TMR门具有更好的容忍MET,除了一些逻辑门。我们在UMC 65 nm工艺中采用非硬化、GDMR和TMR技术实现了几种逻辑门和一个基准电路(C17),并对它们进行了比较。我们对各种逻辑门的模拟表明,GDMR门与TMR门相比,功耗降低约50%,面积减少3倍,延迟减少约50%,然而,GDMR在对MET的容错性方面优于TMR约3倍,除了一些门。对于在UMC 65 nm上实现的C17 ISCAS-85 Benchmark电路,我们发现GDMR实现比TMR实现节省约58%的面积,具有减少31%的延迟,减少19%的功耗和减少32%的错误概率。
Abstract—Circuits designed for space applications need specialconsideration to tolerate radiations. Guarded dual modularredundancy (GDMR), a radiation hardened by design (RHBD)technique for single event transients (SETs) is presented in thispaper. We present a neat mathematical procedure that capturesthe effects of multiple event transients (METs) in any givenradiation-hard by design (RHBD) technique. We analyze the effectiveness of GDMR multiple event transients (METs) againstthe well-known triple-modular redundancy (TMR) techniqueusing this procedure. Our results show that GDMR logic gatesexhibit far better tolerance to METs as compared to TMR gates,except for some logic gates. We have implemented several logicgates and a benchmark circuit (C17) using unhardened, GDMRand TMR techniques in UMC 65nm technology and comparedthem. Our simulations of various logic gates show that GDMRgates consume about 50% less power, 3x less area, and about 50% less delay compared to their TMR counterparts, and yet, GDMR outperforms TMR in terms of error-tolerance to METs by about 3x, except for some gates. For C17 ISCAS-85 Benchmark circuit implemented in UMC 65nm, we find that GDMR implementation consumes about 58% less area, has 31% less delay, 19% less power and 32% less probability of error due to METs than TMR implementation.