PLL On-Chip Jitter Measurement: Analysis and Design
PLL On-Chip Jitter Measurement: Analysis and Design
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PLL 片上抖动测量：分析和设计
DOI：
10.1109/vlsic.2006.1705318
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发表时间：
2006
期刊：
影响因子：
--
通讯作者：
B. Nikolić
中科院分区：
文献类型：
--
作者：
S. Vamvakos;V. Stojanović;J. Zerbe;C. Werner;D. Draper;B. Nikolić
基于死区方法的片上抖动测量的分析揭示了抖动方差估计中的潜在大误差，当抖动分布变化或先验未知时。为了克服这个问题，提出了一种更精确的方差估计方法，并进行了实验验证。PLL和测量电路之间的相关噪声引起的残余误差被充分表征，并且电路拓扑被提出以减轻这种类型的误差
Analysis of on-chip jitter measurements based on the dead-zone method reveals potentially large errors in the jitter variance estimate, when the jitter distribution is changing or not known a priori. To overcome this, a more accurate variance estimation method is proposed and experimentally verified. The residual error, caused by the correlated noise between the PLL and the measurement circuit, is fully characterized and circuit topologies are proposed to mitigate this type of error