InterLock: An Intercorrelated Logic and Routing Locking
InterLock: An Intercorrelated Logic and Routing Locking
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DOI：
10.1145/3400302.3415667
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发表时间：
2020-09
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通讯作者：
Hadi Mardani Kamali;K. Z. Azar;H. Homayoun;Avesta Sasan
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文献类型：
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作者：
Hadi Mardani Kamali;K. Z. Azar;H. Homayoun;Avesta Sasan
在本文中，我们提出了一种规范的修剪和 SAT (CP&SAT) 攻击，用于破坏最先进的基于路由的混淆技术。在CP&SAT攻击中，我们首先基于适合详细路由约束的高效SAT编码机制对密钥可编程路由块（keyRB）进行编码，然后使用有界变量加法（BVA）算法有效地重新编码和减少与keyRB对应的CNF。在 CP&SAT 攻击中，这是在电路遭受 SAT 攻击之前完成的。我们说明这种编码和基于 BVA 的预处理显着减小了与基于路由的混淆电路相对应的 CNF 的大小，结果我们观察到突破现有技术的基于路由的混淆技术的成功率为 100%。此外，我们提出了一种新的互相关逻辑和路由锁定技术，或简称 InterLock，作为减轻 CP&SAT 攻击的对策。在 Interlock 中，除了隐藏连接之外，所选时序路径中的部分逻辑（门）也在 keyRB 中实现。我们说明，当逻辑门与 keyRB 混合时，BVA 作为预处理步骤无法提供任何优势。我们的实验结果表明，通过使用 InterLock，只需三个 8×8 或两个 16×16 keyRB（与实际逻辑门扭曲），就可以保证针对现有攻击以及我们新提出的 CP&SAT 攻击的弹性，而平均而言，即使是中等规模的基准电路，延迟/面积开销也小于 10%。
In this paper, we propose a canonical prune-and-SAT (CP&SAT) attack for breaking state-of-the-art routing-based obfuscation techniques. In the CP&SAT attack, we first encode the key-programmable routing blocks (keyRBs) based on an efficient SAT encoding mechanism suited for detailed routing constraints, and then efficiently re-encode and reduce the CNF corresponded to the keyRB using a bounded variable addition (BVA) algorithm. In the CP&SAT attack, this is done before subjecting the circuit to the SAT attack. We illustrate that this encoding and BVA-based pre-processing significantly reduces the size of the CNF corresponded to the routing-based obfuscated circuit, in the result of which we observe 100% success rate for breaking prior art routing-based obfuscation techniques. Further, we propose a new intercorrelated logic and routing locking technique, or in short InterLock, as a countermeasure to mitigate the CP&SAT attack. In Interlock, in addition to hiding the connectivity, a part of the logic (gates) in the selected timing paths are also implemented in the keyRB(s). We illustrate that when the logic gates are twisted with keyRBs, the BVA could not provide any advantage as a pre-processing step. Our experimental results show that, by using InterLock, with only three 8×8 or only two 16×16 keyRBs (twisted with actual logic gates), the resilience against existing attacks as well as our new proposed CP&SAT attack would be guaranteed while, on average, the delay/area overhead is less than 10% for even medium-size benchmark circuits.