Proceedings Design, Automation and Test in Europe Conference and Exhibition
Proceedings Design, Automation and Test in Europe Conference and Exhibition
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欧洲会议及展览设计、自动化和测试论文集
DOI：
10.1109/date.2003.1253577
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发表时间：
2003
期刊：
影响因子：
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通讯作者：
M. Bushnell
中科院分区：
文献类型：
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作者：
Keerthi Heragu;V. Agrawal;M. Bushnell
涉及以下主题： 环境智能 - 愿景和成就；节能存储系统；不确定;功耗感知设计和综合；测试数据压缩；操作系统抽象和目标定位；嵌入式软件论坛；分析模拟系统的抖动和噪声；半导体器件建模与仿真；嵌入式系统调度与分析； DFT 和 BIST 最新进展；模拟和射频建模、仿真和优化；架构层面的综合；可重构计算中的调度；延误检测和诊断； SoC 嵌入式操作系统；片上网络；系统级建模；可重构SoC；模拟和缺陷导向测试；能源感知软件技术；互连建模和信号完整性；系统级仿真；软件优化；布局综合的全局方法；平台设计和IP复用方法；在线测试和自我修复；安全汽车软件开发；混合信号设计技术；低功耗架构； SoC测试；基于SAT的验证；高度集成的通信系统；芯片产业分区；异步电路；协作设计和基于WWW的工具；硬件/软件协同设计优化；测试模式生成；低功耗软件；应用特定的内存合成；计算机辅助设计。
The following topics are dealt with: ambient intelligence - visions and achievements; energy-efficient memory systems; uncertainty; power-aware design and synthesis; test data compression; operating system abstraction and targeting; embedded software forum; analysis of jitter and noise for analogue systems; semiconductor device modelling and simulation; embedded system scheduling and analysis; DFT and BIST recent advances; analogue and RF modelling, simulation and optimisation; architectural level synthesis; scheduling in reconfigurable computing; delay testing and diagnosis; embedded operating systems for SoC; networks-on-chip; system level modelling; reconfigurable SoC; analogue and defect-oriented testing; energy aware software techniques; interconnect modelling and signal integrity; system level simulation; software optimisation; global approaches to layout synthesis; platform design and IP reuse methods; on-line testing and self-repair; safe automotive software development; mixed-signal design techniques; low power architectures; SoC testing; SAT based verification; highly integrated communication systems; chip estate zoning; asynchronous circuits; collaborative design and WWW-based tools; hardware/software codesign optimization; test pattern generation; low power software; application specific memory synthesis; CAD.