Scalable parallel simulation of networks on chip
Scalable parallel simulation of networks on chip
复制标题
片上网络的可扩展并行仿真
DOI：
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
M. Radetzki
中科院分区：
文献类型：
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作者：
Marcus Eggenberger;M. Radetzki
随着不断的小型化，拥有1024个节点的noc将在2020年左右成为现实。这种noc的设计需要有效的仿真技术来评估设计方案并验证功能的正确性。目前的技术状态，顺序模拟，将不再提供可接受的模拟时间。利用仿真计算机的多核和多线程能力进行并行仿真是一种潜在的解决方案。然而，由于需要同步仿真时间和访问共享数据结构，当前的并行技术的可扩展性有限。这项工作提出了一种基于显式模拟任务排序的新方法，以便在任何依赖任务之间模拟最大的独立任务。这可以实现有效的同步，并与动态负载平衡一起减少阻塞时间。在16核仿真机上实现了高达15.5的近线性仿真加速。
With continuing miniaturization, NoCs with 1024 nodes will become realistic around the year 2020. The design of such NoCs requires efficient simulation techniques to evaluate design alternatives and to validate functional correctness. The current state of the art, sequential simulation, will no longer provide acceptable simulation time. Parallel simulation exploiting multicore and multithreading capabilities of simulation computers is a potential solution. However, current parallel techniques suffer from limited scalability due to the need to synchronize simulation time and the access to shared data structures. This work presents a new approach based on an explicit ordering of simulation tasks so that a maximum of independent tasks are simulated between any dependent tasks. This enables efficient synchronization and, together with dynamic load balancing, reduces blocking time. A near-linear simulation speedup of up to 15.5 is achieved on a 16 core simulation machine.