A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits
A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits
复制标题
基于专用测试层和单片 3D 集成电路测试调度的测试设计解决方案
DOI：
--
复制
发表时间：
2019
影响因子：
2.9
通讯作者：
K. Chakrabarty
中科院分区：
文献类型：
--
作者：
Abhishek Koneru;S. Kannan;K. Chakrabarty
与基于三硅壳的3-D集成相比，整体3-D（M3D）的整合具有明显更高的设备密度。我们根据专用测试层为M3D IC提供了一个测试解决方案，该测试层在功能层之间插入。我们评估了与提议的设计（DFT）解决方案相关的成本，并将其与基于IEEE STD的潜在DFT解决方案进行比较。 P1838。我们的结果表明，所提出的DFT解决方案比基于P1838的DFT解决方案更具成本效益，可通过密度进行多种层间层。我们还提供了一种测试调度和优化技术，用于M3D IC的晶状体测试。该提出的技术提供了在功耗和探测垫约束下的测试时间最小的测试时间表。
Monolithic 3-D (M3D) integration has the potential to achieve significantly higher device density compared to 3-D integration based on through-silicon vias. We propose a test solution for M3D ICs based on dedicated test layers, which are inserted between functional layers. We evaluate the cost associated with the proposed design-for-test (DfT) solution and compare it with that for a potential DfT solution based on the IEEE Std. P1838. Our results show that the proposed DfT solution is more cost-efficient than the P1838-based DfT solution for a wide range of interlayer via density. We also present a test scheduling and optimization technique for wafer-level testing of M3D ICs. The proposed technique provides test schedules with minimum test time under power consumption and probe pad constraints.