Impact of Fermi level pinning at polysilicon gate grain boundaries on nano-MOSFET variability: A 3-D simulation study
Impact of Fermi level pinning at polysilicon gate grain boundaries on nano-MOSFET variability: A 3-D simulation study
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多晶硅栅极晶界处的费米能级钉扎对纳米 MOSFET 可变性的影响：3D 模拟研究
DOI：
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
A. Asenov
中科院分区：
文献类型：
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作者：
A. Brown;G. Roy;A. Asenov
在本文中，我们提出了一项 3D 模拟研究，研究沿多晶硅栅极晶界的费米能级钉扎对纳米 MOSFET 可变性的影响。费米能级的钉扎会导致器件之间的变化，具体取决于栅极内晶界的随机图案。我们提出了一种连贯的 3D 模拟方法，证明了统计模拟的必要性。为了说明我们的方法，我们对 30 nm MOSFET 的多晶硅晶界引起的阈值电压变化进行了统计分析
In this paper we present a 3D simulation study of the effect of Fermi level pinning along polysilicon gate grain boundaries on nano-MOSFET variability. Pinning of the Fermi level results in variations between devices depending on the random pattern of grain boundaries within the gate. We present a coherent 3D simulation methodology demonstrating the necessity of statistical simulations. As an illustration of our approach, we have carried out a statistical analysis of the variation in threshold voltage induced by polysilicon grain boundaries for a 30 nm MOSFET